Lines Matching refs:Subtarget
155 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
162 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
171 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
196 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
226 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
242 if (Subtarget.useCRBits()) { in PPCTargetLowering()
245 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
319 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
354 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
359 if (Subtarget.hasVSX()) { in PPCTargetLowering()
364 if (Subtarget.hasFSQRT()) { in PPCTargetLowering()
369 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
410 if (Subtarget.hasSPE()) { in PPCTargetLowering()
418 if (Subtarget.hasSPE()) in PPCTargetLowering()
424 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
425 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && in PPCTargetLowering()
426 Subtarget.hasFRE())) in PPCTargetLowering()
429 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
430 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() && in PPCTargetLowering()
431 Subtarget.hasFRES())) in PPCTargetLowering()
434 if (Subtarget.hasFCPSGN()) { in PPCTargetLowering()
442 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
458 if (Subtarget.hasP9Vector() && Subtarget.isPPC64()) in PPCTargetLowering()
462 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
470 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) { in PPCTargetLowering()
482 if (!Subtarget.useCRBits()) { in PPCTargetLowering()
495 if (!Subtarget.useCRBits()) in PPCTargetLowering()
498 if (Subtarget.hasFPU()) { in PPCTargetLowering()
509 if (!Subtarget.useCRBits()) in PPCTargetLowering()
514 if (Subtarget.hasSPE()) { in PPCTargetLowering()
538 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
595 if (Subtarget.is64BitELFABI()) { in PPCTargetLowering()
606 } else if (Subtarget.is32BitELFABI()) { in PPCTargetLowering()
614 if (Subtarget.is32BitELFABI()) in PPCTargetLowering()
646 if (Subtarget.hasSPE()) { in PPCTargetLowering()
668 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
683 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
689 if (Subtarget.hasSPE()) { in PPCTargetLowering()
699 if (Subtarget.hasFPCVT()) { in PPCTargetLowering()
700 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
721 if (Subtarget.use64BitRegs()) { in PPCTargetLowering()
739 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
746 if (Subtarget.hasVSX()) { in PPCTargetLowering()
753 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
782 if (Subtarget.hasVSX()) { in PPCTargetLowering()
788 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
798 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
871 if (!Subtarget.hasP8Vector()) { in PPCTargetLowering()
895 Subtarget.useCRBits() ? Legal : Expand); in PPCTargetLowering()
913 if (Subtarget.hasAltivec()) in PPCTargetLowering()
917 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
928 if (Subtarget.hasVSX()) { in PPCTargetLowering()
934 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
939 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
977 if (Subtarget.hasVSX()) { in PPCTargetLowering()
980 if (Subtarget.hasP8Vector()) { in PPCTargetLowering()
984 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1035 if (Subtarget.hasP8Vector()) in PPCTargetLowering()
1044 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1071 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1173 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1178 if (Subtarget.hasP9Vector()) { in PPCTargetLowering()
1235 } else if (Subtarget.hasVSX()) { in PPCTargetLowering()
1279 if (Subtarget.hasP9Altivec()) { in PPCTargetLowering()
1280 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
1298 if (Subtarget.hasP10Vector()) { in PPCTargetLowering()
1303 if (Subtarget.pairedVectorMemops()) { in PPCTargetLowering()
1308 if (Subtarget.hasMMA()) { in PPCTargetLowering()
1315 if (Subtarget.has64BitSupport()) in PPCTargetLowering()
1318 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1336 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
1363 if (Subtarget.hasFPCVT()) in PPCTargetLowering()
1366 if (Subtarget.useCRBits()) in PPCTargetLowering()
1375 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1379 if (Subtarget.hasP9Altivec()) { in PPCTargetLowering()
1409 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1416 switch (Subtarget.getCPUDirective()) { in PPCTargetLowering()
1438 if (Subtarget.enableMachineScheduler()) in PPCTargetLowering()
1447 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc || in PPCTargetLowering()
1448 Subtarget.getCPUDirective() == PPC::DIR_E5500) { in PPCTargetLowering()
1455 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) { in PPCTargetLowering()
1473 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive(); in PPCTargetLowering()
1589 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in getByValTypeAlignment()
1590 if (Subtarget.hasAltivec()) in getByValTypeAlignment()
1596 return Subtarget.useSoftFloat(); in useSoftFloat()
1600 return Subtarget.hasSPE(); in hasSPE()
1781 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1890 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in isVPKUDUMShuffleMask() local
1891 if (!Subtarget.hasP8Vector()) in isVPKUDUMShuffleMask()
2801 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2908 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
3007 if (isLoad && usePartialVectorLoads(N, Subtarget)) { in getPreIndexedAddressParts()
3069 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget, in getLabelAccessInfo() argument
3112 const bool Is64Bit = Subtarget.isPPC64(); in getTOCEntry()
3115 : Subtarget.isAIXABI() in getTOCEntry()
3133 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerConstantPool()
3134 if (Subtarget.isUsingPCRelativeCalls()) { in LowerConstantPool()
3148 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerConstantPool()
3150 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerConstantPool()
3176 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3183 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3200 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3217 if (Subtarget.isUsingPCRelativeCalls()) { in LowerJumpTable()
3228 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerJumpTable()
3236 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerJumpTable()
3238 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerJumpTable()
3256 if (Subtarget.isUsingPCRelativeCalls()) { in LowerBlockAddress()
3267 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerBlockAddress()
3274 if (Subtarget.is32BitELFABI() && isPositionIndependent()) in LowerBlockAddress()
3281 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerBlockAddress()
3289 if (Subtarget.isAIXABI()) in LowerGlobalTLSAddress()
3335 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressLinux()
3343 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3364 bool IsPCRel = Subtarget.isUsingPCRelativeCalls(); in LowerGlobalTLSAddressLinux()
3396 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3420 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3460 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerGlobalAddress()
3461 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalAddress()
3484 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV); in LowerGlobalAddress()
3486 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerGlobalAddress()
3513 assert(!Subtarget.hasP9Vector() && in LowerSETCC()
3586 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3677 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3689 if (Subtarget.isAIXABI()) in LowerADJUST_TRAMPOLINE()
3748 if (Subtarget.isAIXABI()) in LowerINIT_TRAMPOLINE()
3792 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
3992 if (Subtarget.isAIXABI()) in LowerFormalArguments()
3995 if (Subtarget.is64BitELFABI()) in LowerFormalArguments()
3998 assert(Subtarget.is32BitELFABI()); in LowerFormalArguments()
4053 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_32SVR4()
4077 if (Subtarget.hasP8Vector()) in LowerFormalArguments_32SVR4()
4079 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4085 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
4087 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4110 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) { in LowerFormalArguments_32SVR4()
4116 if (!Subtarget.isLittleEndian()) in LowerFormalArguments_32SVR4()
4170 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_32SVR4()
4275 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerFormalArguments_64SVR4()
4276 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerFormalArguments_64SVR4()
4289 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_64SVR4()
4511 Subtarget.hasP8Vector() in LowerFormalArguments_64SVR4()
4515 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
4607 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_64SVR4()
4744 needStackSlotPassParameters(const PPCSubtarget &Subtarget, in needStackSlotPassParameters() argument
4746 assert(Subtarget.is64BitELFABI()); in needStackSlotPassParameters()
4749 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in needStackSlotPassParameters()
4869 needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
4881 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
4886 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
4903 needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
4905 else if (!CB && needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
5004 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); in EmitTailCallStoreFPAndRetAddr() local
5005 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in EmitTailCallStoreFPAndRetAddr()
5006 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr()
5045 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5140 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerCallResult()
5151 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerCallResult()
5161 if (!Subtarget.isLittleEndian()) in LowerCallResult()
5196 const PPCSubtarget &Subtarget, bool isPatchPoint) { in isIndirectCall() argument
5209 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() && in isIndirectCall()
5217 static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) { in isTOCSaveRestoreRequired() argument
5218 return Subtarget.isAIXABI() || in isTOCSaveRestoreRequired()
5219 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()); in isTOCSaveRestoreRequired()
5224 const PPCSubtarget &Subtarget, in getCallOpcode() argument
5241 RetOpc = isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC in getCallOpcode()
5243 } else if (Subtarget.isUsingPCRelativeCalls()) { in getCallOpcode()
5244 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."); in getCallOpcode()
5246 } else if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI()) in getCallOpcode()
5284 const SDLoc &dl, const PPCSubtarget &Subtarget) { in transformCallee() argument
5285 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI()) in transformCallee()
5304 Subtarget.is32BitELFABI() && !isLocalCallee() && in transformCallee()
5305 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_; in transformCallee()
5308 const TargetMachine &TM = Subtarget.getTargetMachine(); in transformCallee()
5320 if (Subtarget.isAIXABI()) { in transformCallee()
5330 if (Subtarget.isAIXABI()) { in transformCallee()
5393 const PPCSubtarget &Subtarget) { in prepareDescriptorIndirectCall() argument
5422 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors() in prepareDescriptorIndirectCall()
5430 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister(); in prepareDescriptorIndirectCall()
5431 const MCRegister TOCReg = Subtarget.getTOCPointerRegister(); in prepareDescriptorIndirectCall()
5434 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset(); in prepareDescriptorIndirectCall()
5435 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset(); in prepareDescriptorIndirectCall()
5437 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5438 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4; in prepareDescriptorIndirectCall()
5467 assert((!hasNest || !Subtarget.isAIXABI()) && in prepareDescriptorIndirectCall()
5486 const PPCSubtarget &Subtarget) { in buildCallOperands() argument
5487 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands()
5509 if (isTOCSaveRestoreRequired(Subtarget)) { in buildCallOperands()
5510 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in buildCallOperands()
5513 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in buildCallOperands()
5520 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest) in buildCallOperands()
5521 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(), in buildCallOperands()
5543 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) && in buildCallOperands()
5544 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls()) in buildCallOperands()
5545 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT)); in buildCallOperands()
5548 if (CFlags.IsVarArg && Subtarget.is32BitELFABI()) in buildCallOperands()
5552 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in buildCallOperands()
5570 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) || in FinishCall()
5571 Subtarget.isAIXABI()) in FinishCall()
5576 Subtarget, DAG.getTarget(), CB ? CB->isStrictFP() : false); in FinishCall()
5579 Callee = transformCallee(Callee, DAG, dl, Subtarget); in FinishCall()
5580 else if (Subtarget.usesFunctionDescriptors()) in FinishCall()
5582 dl, CFlags.HasNest, Subtarget); in FinishCall()
5589 SPDiff, Subtarget); in FinishCall()
5600 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && in FinishCall()
5650 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall())) in LowerCall()
5652 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in LowerCall()
5669 assert((Subtarget.isUsingPCRelativeCalls() || in LowerCall()
5686 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) && in LowerCall()
5692 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint), in LowerCall()
5694 Subtarget.is64BitELFABI() && in LowerCall()
5698 if (Subtarget.isAIXABI()) in LowerCall()
5702 assert(Subtarget.isSVR4ABI()); in LowerCall()
5703 if (Subtarget.isPPC64()) in LowerCall()
5750 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(), in LowerCall_32SVR4()
5884 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) { in LowerCall_32SVR4()
5885 bool IsLE = Subtarget.isLittleEndian(); in LowerCall_32SVR4()
5971 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerCall_64SVR4()
5972 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerCall_64SVR4()
6000 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_64SVR4()
6119 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes); in LowerCall_64SVR4()
6512 if (isTOCSaveRestoreRequired(Subtarget)) { in LowerCall_64SVR4()
6518 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_64SVR4()
6586 const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>( in CC_AIX() local
6588 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX()
6928 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in LowerFormalArguments_AIX() local
6930 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX()
6942 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_AIX()
7003 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7004 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7080 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in LowerFormalArguments_AIX()
7145 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7146 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7173 EnsureStackAlignment(Subtarget.getFrameLowering(), CallerReservedArea); in LowerFormalArguments_AIX()
7233 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in LowerCall_AIX() local
7244 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_AIX()
7245 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX()
7507 const MCRegister TOCBaseReg = Subtarget.getTOCPointerRegister(); in LowerCall_AIX()
7508 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in LowerCall_AIX()
7509 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7511 Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_AIX()
7544 Outs, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in CanLowerReturn()
7559 (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerReturn()
7586 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerReturn()
7587 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerReturn()
7640 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE()
7661 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex()
7672 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset(); in getReturnAddrFrameIndex()
7684 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex()
7695 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset(); in getFramePointerFrameIndex()
7730 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA()
7872 if (Subtarget.isLittleEndian()) in LowerTRUNCATEVector()
7902 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC()
7912 Subtarget.hasSPE()) in LowerSELECT_CC()
7919 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) { in LowerSELECT_CC()
8045 const PPCSubtarget &Subtarget) { in convertFPToInt() argument
8074 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ); in convertFPToInt()
8077 assert((IsSigned || Subtarget.hasFPCVT()) && in convertFPToInt()
8094 SDValue Tmp = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTForReuse()
8100 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
8101 (IsSigned || Subtarget.hasFPCVT()); in LowerFP_TO_INTForReuse()
8126 MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4); in LowerFP_TO_INTForReuse()
8141 SDValue Conv = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTDirectMove()
8160 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerFP_TO_INT()
8241 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8269 (Subtarget.hasFPCVT() || Op.getValueType() == MVT::i32); in canReuseLoadAddress()
8345 if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2) in directMoveIsProfitable()
8367 const PPCSubtarget &Subtarget, in convertIntToFP() argument
8379 bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT(); in convertIntToFP()
8401 assert(Subtarget.hasFPCVT() && in LowerINT_TO_FPDirectMove()
8409 return convertIntToFP(Op, Mov, DAG, Subtarget); in LowerINT_TO_FPDirectMove()
8461 if (Subtarget.isLittleEndian()) in LowerINT_TO_FPVector()
8476 if (Subtarget.hasP9Altivec()) in LowerINT_TO_FPVector()
8513 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerINT_TO_FP()
8531 if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) && in LowerINT_TO_FP()
8532 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8535 assert((IsSigned || Subtarget.hasFPCVT()) && in LowerINT_TO_FP()
8551 !Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8596 } else if (Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8606 } else if (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8616 } else if (((Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8618 (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8653 SDValue FP = convertIntToFP(Op, Bits, DAG, Subtarget, Chain); in LowerINT_TO_FP()
8657 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8680 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8713 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
8735 SDValue FP = convertIntToFP(Op, Ld, DAG, Subtarget, Chain); in LowerINT_TO_FP()
8738 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
9128 static bool isValidSplatLoad(const PPCSubtarget &Subtarget, const SDValue &Op, in isValidSplatLoad() argument
9131 if (!InputNode || !Subtarget.hasVSX() || !ISD::isUNINDEXEDLoad(InputNode)) in isValidSplatLoad()
9181 HasAnyUndefs, 0, !Subtarget.isLittleEndian()); in LowerBUILD_VECTOR()
9188 Subtarget.hasPrefixInstrs()) { in LowerBUILD_VECTOR()
9232 isValidSplatLoad(Subtarget, Op, NewOpcode)) { in LowerBUILD_VECTOR()
9270 !Subtarget.isLittleEndian() && Subtarget.hasVSX() && in LowerBUILD_VECTOR()
9271 Subtarget.hasLFIWAX())) in LowerBUILD_VECTOR()
9279 if (NumUsesOfInputLD == 1 && Subtarget.isLittleEndian() && in LowerBUILD_VECTOR()
9280 Subtarget.isISA3_1() && ElementSize <= 16) in LowerBUILD_VECTOR()
9285 Subtarget.hasVSX()) { in LowerBUILD_VECTOR()
9305 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
9306 haveEfficientBuildVectorPattern(BVN, Subtarget.hasDirectMove(), in LowerBUILD_VECTOR()
9307 Subtarget.hasP8Vector())) in LowerBUILD_VECTOR()
9333 if (Subtarget.hasPrefixInstrs() && SplatSize == 2) in LowerBUILD_VECTOR()
9337 if (Subtarget.hasPrefixInstrs() && SplatSize == 4) in LowerBUILD_VECTOR()
9342 if (Subtarget.hasP9Vector() && SplatSize == 1) in LowerBUILD_VECTOR()
9445 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1; in LowerBUILD_VECTOR()
9451 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2; in LowerBUILD_VECTOR()
9457 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3; in LowerBUILD_VECTOR()
9548 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTB()
9654 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTH()
9790 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) || in lowerToXXSPLTI32DX()
9802 bool IsLE = Subtarget.isLittleEndian(); in lowerToXXSPLTI32DX()
9879 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerVECTOR_SHUFFLE()
9889 if (InputLoad && Subtarget.hasVSX() && V2.isUndef() && in LowerVECTOR_SHUFFLE()
9909 if ((IsFourByte && Subtarget.hasP9Vector()) || !IsFourByte) { in LowerVECTOR_SHUFFLE()
9946 if (Subtarget.hasP9Vector() && in LowerVECTOR_SHUFFLE()
9965 if (Subtarget.hasPrefixInstrs()) { in LowerVECTOR_SHUFFLE()
9971 if (Subtarget.hasP9Altivec()) { in LowerVECTOR_SHUFFLE()
9980 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
9993 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
10006 if (Subtarget.hasP9Vector()) { in LowerVECTOR_SHUFFLE()
10026 if (Subtarget.hasVSX()) { in LowerVECTOR_SHUFFLE()
10060 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
10081 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
10192 bool &isDot, const PPCSubtarget &Subtarget) { in getVectorCompareInfo() argument
10222 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10234 if (Subtarget.hasP9Altivec()) { in getVectorCompareInfo()
10282 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10301 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10311 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10335 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
10378 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10389 if (Subtarget.hasP9Altivec()) in getVectorCompareInfo()
10431 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10446 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10454 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10487 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
10503 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
10566 if (!Subtarget.hasVSX() || (!Subtarget.hasFloat128() && VT == MVT::f128)) in LowerINTRINSIC_WO_CHAIN()
10616 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget)) in LowerINTRINSIC_WO_CHAIN()
10684 assert(Subtarget.isPPC64() && "Only 64-bit is supported for now."); in LowerINTRINSIC_VOID()
10707 if (!Subtarget.isPPC64()) in LowerBSWAP()
10716 if (Subtarget.isLittleEndian()) in LowerBSWAP()
10843 if (Subtarget.hasP9Vector()) { in LowerINSERT_VECTOR_ELT()
10863 if (Subtarget.isISA3_1()) { in LowerINSERT_VECTOR_ELT()
10864 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
10884 if (Subtarget.isLittleEndian()) { in LowerINSERT_VECTOR_ELT()
10907 assert((VT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorLoad()
10909 assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorLoad()
10926 if (Subtarget.isLittleEndian()) { in LowerVectorLoad()
10953 assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorStore()
10955 assert((StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorStore()
10965 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
11010 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerMUL()
11048 !Subtarget.hasP9Vector()) in LowerFP_ROUND()
11090 if (Subtarget.isLittleEndian()) in LowerFP_EXTEND()
11280 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
11359 if (isa<LoadInst>(Inst) && Subtarget.isPPC64()) in emitTrailingFence()
11378 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitAtomicBinary()
11388 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
11393 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
11550 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in EmitPartwordAtomicBinary()
11568 if (Subtarget.hasPartwordAtomics()) in EmitPartwordAtomicBinary()
11576 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
11577 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitPartwordAtomicBinary()
11763 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjSetJmp()
11764 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo(); in emitEHSjLjSetJmp()
11831 if (Subtarget.is64BitELFABI()) { in emitEHSjLjSetJmp()
11844 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
11846 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
11849 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
11872 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
11875 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
11905 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjLongJmp()
11923 : (Subtarget.isSVR4ABI() && isPositionIndependent() ? PPC::R29 in emitEHSjLjLongJmp()
11986 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
12012 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); in getStackProbeSize()
12038 const bool isPPC64 = Subtarget.isPPC64(); in emitProbedAlloca()
12040 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitProbedAlloca()
12202 if (Subtarget.is64BitELFABI() && in EmitInstrWithCustomInserter()
12204 !Subtarget.isUsingPCRelativeCalls()) { in EmitInstrWithCustomInserter()
12224 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitInstrWithCustomInserter()
12477 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
12479 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
12491 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
12496 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
12582 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
12583 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitInstrWithCustomInserter()
12869 if (Subtarget.hasDirectMove()) { in EmitInstrWithCustomInserter()
13030 static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) { in getEstimateRefinementSteps() argument
13035 int RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3; in getEstimateRefinementSteps()
13047 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))) in getSqrtInputTest()
13076 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX())) in getSqrtResultForDenormInput()
13087 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getSqrtEstimate()
13088 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getSqrtEstimate()
13089 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getSqrtEstimate()
13090 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getSqrtEstimate()
13092 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getSqrtEstimate()
13096 UseOneConstNR = !Subtarget.needsTwoConstNR(); in getSqrtEstimate()
13106 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
13107 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
13108 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
13109 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getRecipEstimate()
13111 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getRecipEstimate()
13128 switch (Subtarget.getCPUDirective()) { in combineRepeatedFPDivisors()
13415 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits"); in DAGCombineTruncBoolExt()
13709 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
13710 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
14366 if (!Subtarget.hasVSX()) in DAGCombineBuildVector()
14389 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
14398 if (Subtarget.isISA3_1()) { in DAGCombineBuildVector()
14436 SubvecIdx = Subtarget.isLittleEndian() ? 1 : 0; in DAGCombineBuildVector()
14438 SubvecIdx = Subtarget.isLittleEndian() ? 0 : 1; in DAGCombineBuildVector()
14455 if (useSoftFloat() || !Subtarget.has64BitSupport()) in combineFPToIntToFP()
14476 if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) { in combineFPToIntToFP()
14508 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) && in combineFPToIntToFP()
14513 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14518 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14525 Subtarget.hasFPCVT()) || in combineFPToIntToFP()
14543 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
14706 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
14708 if (ResVT == MVT::f128 && !Subtarget.hasP9Vector()) in combineStoreFPToInt()
14711 if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() || in combineStoreFPToInt()
14801 const PPCSubtarget &Subtarget) { in fixupShuffleMaskForPermutedSToV() argument
14806 Subtarget.isLittleEndian() ? HalfVec : HalfVec - ValidLaneWidth; in fixupShuffleMaskForPermutedSToV()
14816 const PPCSubtarget &Subtarget) { in getSToVPermuted() argument
14836 ResultInElt -= Subtarget.isLittleEndian() ? 0 : 1; in getSToVPermuted()
14865 bool IsLittleEndian = Subtarget.isLittleEndian(); in combineVectorShuffle()
14872 if (!Subtarget.hasDirectMove()) in combineVectorShuffle()
14934 SToVLHS = getSToVPermuted(SToVLHS, DAG, Subtarget); in combineVectorShuffle()
14944 SToVRHS = getSToVPermuted(SToVRHS, DAG, Subtarget); in combineVectorShuffle()
14956 HalfVec, ValidLaneWidth, Subtarget); in combineVectorShuffle()
15054 if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX()) in combineVReverseMemOP()
15060 if (!Subtarget.hasP9Vector()) in combineVReverseMemOP()
15177 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15212 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
15233 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
15248 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
15314 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
15363 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) && in PerformDAGCombine()
15365 !Subtarget.hasP8Vector() && in PerformDAGCombine()
15372 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
15477 Perm = Subtarget.hasAltivec() in PerformDAGCombine()
15492 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
15541 if (!DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() && in PerformDAGCombine()
15577 if (Subtarget.needsSwapsForVSXMemOps()) { in PerformDAGCombine()
15590 if (Subtarget.needsSwapsForVSXMemOps()) { in PerformDAGCombine()
15605 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
15610 (Subtarget.hasLDBRX() && Is64BitBswapOn64BitTgt))) { in PerformDAGCombine()
15662 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
15785 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) { in PerformDAGCombine()
15852 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
15936 switch (Subtarget.getCPUDirective()) { in getPrefLoopAlignment()
15961 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in getPrefLoopAlignment()
16083 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16087 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16095 if (Subtarget.hasSPE()) { in getRegForInlineAsmConstraint()
16108 if (Subtarget.hasAltivec() && VT.isVector()) in getRegForInlineAsmConstraint()
16110 else if (Subtarget.hasVSX()) in getRegForInlineAsmConstraint()
16117 } else if (Constraint == "wc" && Subtarget.useCRBits()) { in getRegForInlineAsmConstraint()
16122 Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
16127 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16130 } else if ((Constraint == "ws" || Constraint == "ww") && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
16131 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16164 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
16168 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
16183 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
16196 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) { in getRegForInlineAsmConstraint()
16295 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
16344 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR()
16355 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl, in LowerRETURNADDR()
16400 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName()
16419 if (Subtarget.is32BitELFABI()) in isAccessedAsGotIndirect()
16424 if (Subtarget.isAIXABI()) in isAccessedAsGotIndirect()
16438 return Subtarget.isGVIndirectSymbol(G->getGlobal()); in isAccessedAsGotIndirect()
16580 if (Subtarget.hasAltivec() && Op.size() >= 16 && in getOptimalMemOpType()
16582 ((Op.isMemset() && Subtarget.hasVSX()) || Subtarget.hasP8Vector()))) in getOptimalMemOpType()
16586 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
16625 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
16672 !Subtarget.allowsUnalignedFPAccess()) in allowsMisalignedMemoryAccesses()
16676 if (Subtarget.hasVSX()) { in allowsMisalignedMemoryAccesses()
16734 return Subtarget.hasP9Vector(); in isFMAFasterThanFMulAndFAdd()
16807 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
16812 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
16819 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves in shouldExpandBuildVectorWithShuffles()
16821 if (Subtarget.hasVSX()) in shouldExpandBuildVectorWithShuffles()
16828 if (DisableILPPref || Subtarget.enableMachineScheduler()) in getSchedulingPreference()
16921 if (!Subtarget.isTargetLinux()) in useLoadStackGuardNode()
16929 if (Subtarget.isAIXABI()) { in insertSSPDeclarations()
16934 if (!Subtarget.isTargetLinux()) in insertSSPDeclarations()
16939 if (Subtarget.isAIXABI()) in getSDagStackGuard()
16946 if (!VT.isSimple() || !Subtarget.hasVSX()) in isFPImmLegal()
16956 if (Subtarget.hasPrefixInstrs()) { in isFPImmLegal()
17006 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || in combineSHL()
17049 const PPCSubtarget &Subtarget) { in combineADDToADDZE() argument
17050 if (!Subtarget.isPPC64()) in combineADDToADDZE()
17135 const PPCSubtarget &Subtarget) { in combineADDToMAT_PCREL_ADDR() argument
17136 if (!Subtarget.isUsingPCRelativeCalls()) in combineADDToMAT_PCREL_ADDR()
17176 if (auto Value = combineADDToADDZE(N, DCI.DAG, Subtarget)) in combineADD()
17179 if (auto Value = combineADDToMAT_PCREL_ADDR(N, DCI.DAG, Subtarget)) in combineADD()
17197 if (Subtarget.useCRBits()) { in combineTRUNCATE()
17207 if (Subtarget.hasP9Altivec() && Op0.getOpcode() == ISD::ABS) { in combineTRUNCATE()
17268 switch (this->Subtarget.getCPUDirective()) { in combineMUL()
17379 if (!Subtarget.is64BitELFABI()) in mayBeEmittedAsTailCall()
17408 if (!Subtarget.hasVSX()) in hasBitPreservingFPLogic()
17410 if (Subtarget.hasP9Vector() && VT == MVT::f128) in hasBitPreservingFPLogic()
17440 assert(Subtarget.hasP9Altivec() && in combineABS()
17484 assert(Subtarget.hasP9Altivec() && in combineVSelect()
17663 if (!Subtarget.hasP9Vector()) in computeMOFlags()
17667 if (Subtarget.hasPrefixInstrs()) in computeMOFlags()
17670 if (Subtarget.hasSPE()) in computeMOFlags()
17680 if (Subtarget.isISA3_1() && ((ParentOp == ISD::INTRINSIC_W_CHAIN) || in computeMOFlags()
17718 assert(Subtarget.pairedVectorMemops() && in computeMOFlags()
17802 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
17972 assert(Subtarget.isUsingPCRelativeCalls() && in SelectOptimalAddrMode()
18023 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18079 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18102 return Subtarget.isPPC64() && in shouldInlineQuadwordAtomics()
18103 (EnableQuadwordAtomics || !Subtarget.getTargetTriple().isOSAIX()) && in shouldInlineQuadwordAtomics()
18104 Subtarget.hasQuadwordAtomics(); in shouldInlineQuadwordAtomics()