Lines Matching refs:Subtarget
105 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 in getRegisterTypeForCallingConv()
113 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64); in getNumRegistersForCallingConv()
289 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { in MipsTargetLowering()
296 if (Subtarget.hasMips32r6()) in MipsTargetLowering()
351 if (Subtarget.isGP64bit()) { in MipsTargetLowering()
366 if (!Subtarget.isGP64bit()) { in MipsTargetLowering()
373 if (Subtarget.isGP64bit()) in MipsTargetLowering()
399 if (Subtarget.hasCnMips()) { in MipsTargetLowering()
413 if (!Subtarget.hasMips32r2()) in MipsTargetLowering()
416 if (!Subtarget.hasMips64r2()) in MipsTargetLowering()
453 if (!Subtarget.isGP64bit()) { in MipsTargetLowering()
458 if (!Subtarget.hasMips32r2()) { in MipsTargetLowering()
464 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) in MipsTargetLowering()
466 if (!Subtarget.hasMips64()) in MipsTargetLowering()
469 if (!Subtarget.hasMips32r2()) in MipsTargetLowering()
471 if (!Subtarget.hasMips64r2()) in MipsTargetLowering()
474 if (Subtarget.isGP64bit()) { in MipsTargetLowering()
496 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); in MipsTargetLowering()
507 isMicroMips = Subtarget.inMicroMipsMode(); in MipsTargetLowering()
527 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && in createFastISel()
528 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && in createFastISel()
529 !Subtarget.inMicroMipsMode(); in createFastISel()
534 Subtarget.useXGOT()) in createFastISel()
549 const MipsSubtarget &Subtarget) { in performDivRemCombine() argument
658 const MipsSubtarget &Subtarget) { in performSELECTCombine() argument
739 const MipsSubtarget &Subtarget) { in performCMovFPCombine() argument
766 const MipsSubtarget &Subtarget) { in performANDCombine() argument
767 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
805 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { in performANDCombine()
849 const MipsSubtarget &Subtarget) { in performORCombine() argument
854 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
905 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || in performORCombine()
946 const MipsSubtarget &Subtarget) { in performMADD_MSUBCombine() argument
984 if (Subtarget.hasMips64()) in performMADD_MSUBCombine()
1048 const MipsSubtarget &Subtarget) { in performSUBCombine() argument
1051 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && in performSUBCombine()
1052 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) in performSUBCombine()
1053 return performMADD_MSUBCombine(N, DAG, Subtarget); in performSUBCombine()
1063 const MipsSubtarget &Subtarget) { in performADDCombine() argument
1066 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && in performADDCombine()
1067 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) in performADDCombine()
1068 return performMADD_MSUBCombine(N, DAG, Subtarget); in performADDCombine()
1095 const MipsSubtarget &Subtarget) { in performSHLCombine() argument
1100 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) in performSHLCombine()
1154 return performDivRemCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1156 return performSELECTCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1159 return performCMovFPCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1161 return performANDCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1163 return performORCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1165 return performADDCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1167 return performSHLCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1169 return performSUBCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1176 return Subtarget.hasMips32(); in isCheapToSpeculateCttz()
1180 return Subtarget.hasMips32(); in isCheapToSpeculateCtlz()
1410 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, in EmitInstrWithCustomInserter()
1420 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); in EmitInstrWithCustomInserter()
1427 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); in EmitInstrWithCustomInserter()
1469 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitAtomicBinary()
1623 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitSignExtendToI32InReg()
1626 if (Subtarget.hasMips32r2() && Size == 1) { in emitSignExtendToI32InReg()
1631 if (Subtarget.hasMips32r2() && Size == 2) { in emitSignExtendToI32InReg()
1661 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitAtomicBinaryPartword()
1791 if (Subtarget.isLittle()) { in emitAtomicBinaryPartword()
1854 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitAtomicCmpSwap()
1909 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitAtomicCmpSwapPartword()
1978 if (Subtarget.isLittle()) { in emitAtomicCmpSwapPartword()
2029 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); in lowerBRCOND()
2049 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); in lowerSELECT()
2061 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); in lowerSETCC()
2090 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) in lowerGlobalAddress()
2109 if (Subtarget.useXGOT()) in lowerGlobalAddress()
2127 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) in lowerBlockAddress()
2222 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) in lowerJumpTable()
2244 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) in lowerConstantPool()
2315 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { in lowerVAARG()
2423 if (Subtarget.isGP64bit()) in lowerFCOPYSIGN()
2424 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); in lowerFCOPYSIGN()
2426 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); in lowerFCOPYSIGN()
2434 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode()) in lowerFABS32()
2474 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode()) in lowerFABS64()
2495 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert()); in lowerFABS()
2497 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert()); in lowerFABS()
2582 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; in lowerShiftLeftParts()
2615 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; in lowerShiftRightParts()
2644 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { in lowerShiftRightParts()
2646 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 in lowerShiftRightParts()
2683 if (Subtarget.systemSupportsUnalignedAccess()) in lowerLOAD()
2691 bool IsLittle = Subtarget.isLittle(); in lowerLOAD()
2810 if (!Subtarget.systemSupportsUnalignedAccess() && in lowerSTORE()
2813 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); in lowerSTORE()
2815 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); in lowerSTORE()
2831 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) in lowerFP_TO_SINT()
2867 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( in CC_MipsO32() local
2883 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { in CC_MipsO32()
3076 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getOpndList()
3080 if (Subtarget.inMips16HardFloat()) { in getOpndList()
3113 Subtarget.inMips16Mode() || in AdjustInstrPostInstrSelection()
3170 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); in LowerCall()
3178 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); in LowerCall()
3287 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), in LowerCall()
3308 if (!Subtarget.isLittle()) in LowerCall()
3394 if (!Subtarget.isABICalls() && !IsPIC) { in LowerCall()
3399 if (Subtarget.useLongCalls()) in LowerCall()
3400 Callee = Subtarget.hasSym32() in LowerCall()
3404 bool UseLongCalls = Subtarget.useLongCalls(); in LowerCall()
3414 Callee = Subtarget.hasSym32() in LowerCall()
3427 else if (Subtarget.useXGOT()) { in LowerCall()
3449 else if (Subtarget.useXGOT()) { in LowerCall()
3708 if (!Subtarget.isLittle()) in LowerFormalArguments()
3725 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) in LowerFormalArguments()
3987 if (Subtarget.hasMSA() && type->isVectorTy() && in getSingleConstraintMatchWeight()
4042 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; in getTypeForExtReturn()
4050 Subtarget.getRegisterInfo(); in parseRegForInlineAsmConstraint()
4100 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; in parseRegForInlineAsmConstraint()
4134 if (Subtarget.inMips16Mode()) in getRegForInlineAsmConstraint()
4138 if (VT == MVT::i64 && !Subtarget.isGP64bit()) in getRegForInlineAsmConstraint()
4140 if (VT == MVT::i64 && Subtarget.isGP64bit()) in getRegForInlineAsmConstraint()
4155 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { in getRegForInlineAsmConstraint()
4156 if (Subtarget.isFP64bit()) in getRegForInlineAsmConstraint()
4318 if (Subtarget.hasMips64()) in getOptimalMemOpType()
4343 return Subtarget.useSoftFloat(); in useSoftFloat()
4354 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); in copyByValRegs()
4408 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); in passByValArg()
4501 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); in writeVarArgRegs()
4544 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); in HandleByVal()
4554 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); in HandleByVal()
4591 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && in emitPseudoSELECT()
4596 Subtarget.getInstrInfo(); in emitPseudoSELECT()
4668 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && in emitPseudoD_SELECT()
4672 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitPseudoD_SELECT()
4747 if (Subtarget.isGP64bit()) { in getRegisterByName()
4769 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitLDR_W()
4770 const bool IsLittle = Subtarget.isLittle(); in emitLDR_W()
4779 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitLDR_W()
4815 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitLDR_D()
4816 const bool IsLittle = Subtarget.isLittle(); in emitLDR_D()
4825 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitLDR_D()
4827 if (Subtarget.isGP64bit()) { in emitLDR_D()
4899 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitSTR_W()
4900 const bool IsLittle = Subtarget.isLittle(); in emitSTR_W()
4909 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitSTR_W()
4949 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitSTR_D()
4950 const bool IsLittle = Subtarget.isLittle(); in emitSTR_D()
4959 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitSTR_D()
4961 if (Subtarget.isGP64bit()) { in emitSTR_D()