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Searched refs:SubIdx (Results 1 – 25 of 60) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp236 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
240 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
242 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
260 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
261 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
310 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
312 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
316 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
319 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
323 DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
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H A DExpandPostRAPseudos.cpp91 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
93 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
94 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
H A DTargetRegisterInfo.cpp112 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg() argument
113 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
133 if (SubIdx) { in printReg()
135 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
137 OS << ":sub(" << SubIdx << ')'; in printReg()
H A DPeepholeOptimizer.cpp464 unsigned SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
465 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
478 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
488 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
514 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
608 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1928 if (RegSeqInput.SubIdx == DefSubReg) in getNextSourceFromRegSequence()
1965 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
1984 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none()) in getNextSourceFromInsertSubreg()
2017 ExtractSubregInputReg.SubIdx); in getNextSourceFromExtractSubreg()
H A DRegisterCoalescer.cpp1746 unsigned SubIdx) { in updateRegDefsUses() argument
1783 if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr()) in updateRegDefsUses()
1793 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1804 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1824 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
2338 const unsigned SubIdx; member in __anoncc82f7ba0311::JoinVals
2507 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
2570 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes()
2876 LaneBitmask OtherMask = TRI->getSubRegIndexLaneMask(Other.SubIdx); in analyzeValue()
3029 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in usesLanes()
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H A DTargetInstrInfo.cpp388 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
392 if (!SubIdx) { in getStackSlotRange()
397 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
402 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
419 Register DestReg, unsigned SubIdx, in reMaterialize() argument
423 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1314 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
1342 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
H A DMachineOperand.cpp75 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg() argument
78 if (SubIdx && getSubReg()) in substVirtReg()
79 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
81 if (SubIdx) in substVirtReg()
82 setSubReg(SubIdx); in substVirtReg()
H A DMachineVerifier.cpp1880 if (unsigned SubIdx = MI->getOperand(2).getSubReg()) in visitMachineInstrBefore() local
1881 InsertedSize = TRI->getSubRegIdxSize(SubIdx); in visitMachineInstrBefore()
2018 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
2021 if (SubIdx) { in visitMachineOperand()
2100 if (SubIdx) { in visitMachineOperand()
2123 if (SubIdx) { in visitMachineOperand()
2125 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
2129 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
2135 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
2142 if (SubIdx) { in visitMachineOperand()
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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp131 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
132 SubIdx->computeConcatTransitiveClosure(); in computeConcatTransitiveClosure()
138 if (SubIdx->ConcatenationOf.empty()) { in computeConcatTransitiveClosure()
144 I += SubIdx->ConcatenationOf.size(); in computeConcatTransitiveClosure()
535 if (!SubIdx) in computeSecondarySubRegs()
1111 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1893 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1897 if (SuperIdx == SubIdx) in pruneUnitSets()
1918 SuperSetIDs.push_back(SubIdx); in pruneUnitSets()
2256 if (SubIdx.Artificial) in inferSubClassWithSubReg()
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H A DCodeGenRegisters.h381 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
382 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
395 const CodeGenSubRegIndex *SubIdx) const;
397 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
399 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
404 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
408 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
410 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
H A DRegisterBankEmitter.cpp197 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses() local
199 PossibleSubclass.getSuperRegClasses(&SubIdx, BV); in visitRegisterBankClasses()
H A DGlobalISelEmitter.cpp4680 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); in createAndImportSubInstructionRenderer() local
4681 if (!SubIdx) in createAndImportSubInstructionRenderer()
4725 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in createAndImportSubInstructionRenderer() local
4726 if (!SubIdx) in createAndImportSubInstructionRenderer()
4848 RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx); in importExplicitUseRenderers()
4856 SubIdx); in importExplicitUseRenderers()
4885 DstMIBuilder.addRenderer<SubRegIndexRenderer>(SubIdx); in importExplicitUseRenderers()
5374 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); in runOnPattern() local
5375 if (!SubIdx) in runOnPattern()
5458 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in runOnPattern() local
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H A DCodeGenTarget.h113 const CodeGenSubRegIndex *SubIdx,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h368 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
369 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
371 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
378 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
379 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
380 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
588 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
590 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1289 unsigned SubIdx = 0,
H A DTargetInstrInfo.h249 Register &DstReg, unsigned &SubIdx) const { in isCoalescableExtInstr() argument
350 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
399 unsigned SubIdx, const MachineInstr &Orig,
506 unsigned SubIdx; member
509 unsigned SubIdx = 0)
510 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TileConfig.cpp178 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; in INITIALIZE_PASS_DEPENDENCY() local
181 SubIdx = 0; in INITIALIZE_PASS_DEPENDENCY()
190 .addReg(R, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
H A DX86InstructionSelector.cpp209 SubIdx = X86::sub_32bit; in getSubRegIndex()
211 SubIdx = X86::sub_16bit; in getSubRegIndex()
213 SubIdx = X86::sub_8bit; in getSubRegIndex()
216 return SubIdx; in getSubRegIndex()
745 unsigned SubIdx; in selectTruncOrPtrToInt() local
750 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
754 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
1167 SubIdx = X86::sub_xmm; in emitExtractSubreg()
1169 SubIdx = X86::sub_ymm; in emitExtractSubreg()
1206 SubIdx = X86::sub_xmm; in emitInsertSubreg()
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H A DX86InstrInfo.h190 Register &DstReg, unsigned &SubIdx) const override;
245 Register DestReg, unsigned SubIdx,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
H A DThumbRegisterInfo.h41 const DebugLoc &dl, Register DestReg, unsigned SubIdx,
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCRegisterInfo.cpp24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp450 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg() argument
453 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
518 SubIdx == DefSubIdx && in EmitSubregNode()
534 Reg = ConstrainForSubReg(Reg, SubIdx, in EmitSubregNode()
546 CopyMI.addReg(Reg, 0, SubIdx); in EmitSubregNode()
548 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); in EmitSubregNode()
555 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
573 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
594 MIB.addImm(SubIdx); in EmitSubregNode()
654 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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H A DInstrEmitter.h87 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h254 unsigned SubIdx) const;
263 unsigned SubIdx) const;
H A DSIInstrInfo.cpp676 int16_t SubIdx = BaseIndices[Idx]; in expandSGPRCopy() local
1002 unsigned SubIdx; in copyPhysReg() local
1004 SubIdx = SubIndices[Idx]; in copyPhysReg()
2854 .addReg(FalseReg, 0, SubIdx) in insertSelect()
2855 .addReg(TrueReg, 0, SubIdx); in insertSelect()
2859 .addReg(TrueReg, 0, SubIdx) in insertSelect()
2867 .addImm(SubIdx); in insertSelect()
4904 .addReg(NewSuperReg, 0, SubIdx); in buildExtractSubReg()
4914 unsigned SubIdx, in buildExtractSubRegOrImm() argument
4917 if (SubIdx == AMDGPU::sub0) in buildExtractSubRegOrImm()
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