CodeGen: Remove AliasAnalysis from regalloc

This was stored in LiveIntervals, but not actually used for anything
related to LiveIntervals. It was only used in one check for if a load
instruction is

CodeGen: Remove AliasAnalysis from regalloc

This was stored in LiveIntervals, but not actually used for anything
related to LiveIntervals. It was only used in one check for if a load
instruction is rematerializable. I also don't think this was entirely
correct, since it was implicitly assuming constant loads are also
dereferenceable.

Remove this and rely only on the invariant+dereferenceable flags in
the memory operand. Set the flag based on the AA query upfront. This
should have the same net benefit, but has the possible disadvantage of
making this AA query nonlazy.

Preserve the behavior of assuming pointsToConstantMemory implying
dereferenceable for now, but maybe this should be changed.

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[CodeGen] Qualify auto variables in for loops (NFC)

[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments

[CodeGen] Use range-based for loops (NFC)

[llvm] Use range-based for loops (NFC)

[llvm] Use make_early_inc_range (NFC)

[CodeGen] Use make_early_inc_range (NFC)

[CodeGen] RegisterCoalescer::buildVRegToDbgValueMap - use const-ref value in for-range loop. NFCI.

Avoid unnecessary copies, reported by MSVC static analyzer.

[RegisterCoalescer] Make resolveConflicts aware of earlyclobber

Prior to this patch, it skipped the instruction defining VNI when checking if the tainted lanes are used.
In the given example, VRGATH

[RegisterCoalescer] Make resolveConflicts aware of earlyclobber

Prior to this patch, it skipped the instruction defining VNI when checking if the tainted lanes are used.
In the given example, VRGATHER is an illegal instruction because its DstReg overlaps with SrcReg.

Therefore we need to check the defining instruction as well when there is an earlyclobber constraint.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D105684

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Prevent dead uses in register coalescer after rematerialization

The coalescer does not check if register uses are available
at the point of rematerialization. If it attempts to rematerialize
an inst

Prevent dead uses in register coalescer after rematerialization

The coalescer does not check if register uses are available
at the point of rematerialization. If it attempts to rematerialize
an instruction with such uses it can end up with use without a def.

LiveRangeEdit does such check during rematerialization, so just
call LiveRangeEdit::allUsesAvailableAt() to avoid the problem.

Differential Revision: https://reviews.llvm.org/D106396

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[RegisterCoalescer] Resolve conflict based on liveness of subregister

Currently we are resolving lane/subregister conflict by visiting
instructions sequentially in current block to see whether there

[RegisterCoalescer] Resolve conflict based on liveness of subregister

Currently we are resolving lane/subregister conflict by visiting
instructions sequentially in current block to see whether there is any
use of the tainted lanes. To save compile time, we are not doing further
check in successor blocks. This sounds reasonable without subgregister liveness.

But since we have added subregister liveness tracking capability to
register coalescer, we can easily determine whether we have subregister
liveness conflict by checking subranges. This would help coalescing more
COPYs for target that enables subregister liveness tracking.

Reviewed by: arsenm, qcolombet

Differential Revision: https://reviews.llvm.org/D104509

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[DebugInfo][InstrRef][4/4] Support DBG_INSTR_REF through all backend passes

This is a cleanup patch -- we're now able to support all flavours of
variable location in instruction referencing mode. Th

[DebugInfo][InstrRef][4/4] Support DBG_INSTR_REF through all backend passes

This is a cleanup patch -- we're now able to support all flavours of
variable location in instruction referencing mode. This patch updates
various tests for debug instructions to be broader: numerous code paths
try to ignore debug isntructions, and they now have to ignore the
additional DBG_PHI and DBG_INSTR_REFs that we can generate.

A small amount of rework happens for LiveDebugVariables: as we don't need
to track live intervals through regalloc any more, we can get away with
unlinking debug instructions before regalloc, then re-inserting them after.
Note that this isn't (yet) true of DBG_VALUE_LISTs, they still have to go
through live interval tracking.

In SelectionDAG, add a helper lambda that emits half-formed DBG_INSTR_REFs
for arguments in instr-ref mode, DBG_VALUE otherwise. This is one of the
final locations where DBG_VALUEs are emitted for vreg arguments.

X86InstrInfo now un-sets the debug instr number on SUB instructions that
get mutated into CMP instructions. As the instruction no longer computes a
subtraction, we can't use it for variable locations.

Differential Revision: https://reviews.llvm.org/D88898

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RegisterCoalescer: Fix iterating through use operands.

Fixes a minor bug when trying to iterate through use operands when
updating debug use operands.

Extends a test to include above.

Differential

RegisterCoalescer: Fix iterating through use operands.

Fixes a minor bug when trying to iterate through use operands when
updating debug use operands.

Extends a test to include above.

Differential Revision: https://reviews.llvm.org/D104576

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Re-land ae4303b42c, "Track PHI values through register coalescing"

Was reverted in 0507fc2ffc9, in phi-coalesce-subreg.mir I'd explicitly named
some passes to run instead of specifying a range. As a

Re-land ae4303b42c, "Track PHI values through register coalescing"

Was reverted in 0507fc2ffc9, in phi-coalesce-subreg.mir I'd explicitly named
some passes to run instead of specifying a range. As a result some
two-address-instrs weren't correctly rewritten and the verifier got upset.
Original commit message:

[DebugInstrRef][2/3] Track PHI values through register coalescing

In the instruction referencing variable location model, we store variable
locations that point at PHIs in MachineFunction during register allocation.
Unfortunately, register coalescing can substantially change the locations
of registers, and so that PHI-variable-location side table needs
maintenence during the pass.

This patch builds an index from the side table, and whenever a vreg gets
coalesced into another vreg, update the index to record the new vreg that
the PHI happens in. It also accepts a limited range of subregister
coalescing, for example merging a subregister into a larger class.

Differential Revision: https://reviews.llvm.org/D86813

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Revert "[DebugInstrRef][2/3] Track PHI values through register coalescing"

This reverts commit ae4303b42cfa5c8c14e3fff67d73af2f154aea9a.

Expensive checks buildbot has found a problem with this:

Revert "[DebugInstrRef][2/3] Track PHI values through register coalescing"

This reverts commit ae4303b42cfa5c8c14e3fff67d73af2f154aea9a.

Expensive checks buildbot has found a problem with this:

https://lab.llvm.org/buildbot/#/builders/16/builds/11863

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[DebugInstrRef][2/3] Track PHI values through register coalescing

In the instruction referencing variable location model, we store variable
locations that point at PHIs in MachineFunction during reg

[DebugInstrRef][2/3] Track PHI values through register coalescing

In the instruction referencing variable location model, we store variable
locations that point at PHIs in MachineFunction during register
allocation. Unfortunately, register coalescing can substantially change
the locations of registers, and so that PHI-variable-location side table
needs maintenence during the pass.

This patch builds an index from the side table, and whenever a vreg gets
coalesced into another vreg, update the index to record the new vreg that
the PHI happens in. It also accepts a limited range of subregister
coalescing, for example merging a subregister into a larger class.

Differential Revision: https://reviews.llvm.org/D86813

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[CSSPGO] Exclude pseudo probes from slot index

Pseudo probe are currently given a slot index like other regular instructions. This affects register pressure and lifetime weight computation because o

[CSSPGO] Exclude pseudo probes from slot index

Pseudo probe are currently given a slot index like other regular instructions. This affects register pressure and lifetime weight computation because of enlarged lifetime length with pseudo probe instructions. As a consequence, program could get different code generated w/ and w/o pseudo probes. I'm closing the gap by excluding pseudo probes from stack index and downstream register allocation related passes.

Reviewed By: wmi

Differential Revision: https://reviews.llvm.org/D100334

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[DebugInfo] Handle DBG_VALUES with multiple variable location operands in MIR

This patch adds handling for DBG_VALUE_LIST in the MIR-passes (after
finalize-isel), excluding the debug liveness passes

[DebugInfo] Handle DBG_VALUES with multiple variable location operands in MIR

This patch adds handling for DBG_VALUE_LIST in the MIR-passes (after
finalize-isel), excluding the debug liveness passes and DWARF emission. This
most significantly affects MachineSink, which now needs to consider all used
registers of a debug value when sinking, but for most passes this change is
simply replacing getDebugOperand(0) with an iteration over all debug operands.

Differential Revision: https://reviews.llvm.org/D92578

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[CodeGen] Use range-based for loops (NFC)

RegisterCoalescer: Fix not setting undef on coalesced subregister uses

This was only adding undef to the use if the copy itself had a
subregister index. It did not consider the subrange liveness if

RegisterCoalescer: Fix not setting undef on coalesced subregister uses

This was only adding undef to the use if the copy itself had a
subregister index. It did not consider the subrange liveness if the
use had a subreg index to begin with.

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RegisterCoalescer: Prune undef subranges from copy pairs in loops

If we had a pair of copies inside a loop which introduced new liveness
to a subregister which was undef before the loop, we would ha

RegisterCoalescer: Prune undef subranges from copy pairs in loops

If we had a pair of copies inside a loop which introduced new liveness
to a subregister which was undef before the loop, we would have a
dummy phi-only segment remaining across the loop body. Later, this
false segment would confuse RenameIndependentSubregs causing it to
introduce IMPLICIT_DEFs with broken value numbering.

It seems always adding the lanes to ShrinkMask is OK, so any
conditions should be purely a compile time filter.

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[NFC] Refine some uninitialized used variables.

These warning are reported by static code analysis tool: Klocwork

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D95421

RegisterCoalescer: Remove phi-only subranges when erasing identity copies

Undef subranges are not present in the live range values, except when
they cross block boundaries. In this situation, a iden

RegisterCoalescer: Remove phi-only subranges when erasing identity copies

Undef subranges are not present in the live range values, except when
they cross block boundaries. In this situation, a identity copy is
inside a loop, and one of the lanes is undefined. It only appears
alive inside the loop due to the copy. Once the copy was erased, it
would leave behind a segment inside the loop body with no
corresponding def anywhere in the program.

When RenameIndependentSubregs processed this dummy interval, it would
introduce a "Multiple connected components in live interval" verifier
error when IMPLICIT_DEFs were added to the other two blocks. I believe
there is a missing verifier check for this type of dummy interval.

I have found additional cases from the same fundamental problem in
other areas I haven't managed to fix yet (e.g. the commented out
prune_subrange_phi_value_* cases).

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[NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister.

Typing the API appropriately.

Differential Revision: https://reviews.llvm.org/D92341

RegisterCoalescer: Use Register