450 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,  in ConstrainForSubReg()  argument
453   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);  in ConstrainForSubReg()
466   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);  in ConstrainForSubReg()
499     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();  in EmitSubregNode()  local
518         SubIdx == DefSubIdx &&  in EmitSubregNode()
534         Reg = ConstrainForSubReg(Reg, SubIdx,  in EmitSubregNode()
546         CopyMI.addReg(Reg, 0, SubIdx);  in EmitSubregNode()
548         CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));  in EmitSubregNode()
555     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();  in EmitSubregNode()  local
573     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);  in EmitSubregNode()
594     MIB.addImm(SubIdx);  in EmitSubregNode()
654         unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();  in EmitRegSequence()  local
658         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);  in EmitRegSequence()