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Searched refs:SrcReg (Results 1 – 25 of 197) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) in getCRFromCRBit()
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) in getCRFromCRBit()
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) in getCRFromCRBit()
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) in getCRFromCRBit()
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H A DPPCFastISel.cpp750 if (SrcReg == 0) in SelectStore()
965 if (!SrcReg) in SelectFPExt()
983 if (!SrcReg) in SelectFPTrunc()
1000 SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg); in SelectFPTrunc()
1026 SrcReg = TmpReg; in PPCMoveToFPReg()
1084 if (SrcReg == 0) in SelectIToFP()
1122 SrcReg = TmpReg; in SelectIToFP()
1211 if (SrcReg == 0) in SelectFPToI()
1218 SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg); in SelectFPToI()
1220 SrcReg = copyRegToRegClass(&PPC::VSFRCRegClass, SrcReg); in SelectFPToI()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp136 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
142 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction() local
157 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
173 Register SrcReg = Src1.getReg(); in runOnMachineFunction() local
175 std::make_pair(*&SrcReg, Hexagon::isub_hi); in runOnMachineFunction()
184 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
190 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
206 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
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/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DKnownBitsTest.cpp1140 Register SrcReg; in TEST_F() local
1145 Res = Info.getKnownBits(SrcReg); in TEST_F()
1152 Res = Info.getKnownBits(SrcReg); in TEST_F()
1159 Res = Info.getKnownBits(SrcReg); in TEST_F()
1639 Register SrcReg; in TEST_F() local
1645 Res = Info.getKnownBits(SrcReg); in TEST_F()
1653 Res = Info.getKnownBits(SrcReg); in TEST_F()
1661 Res = Info.getKnownBits(SrcReg); in TEST_F()
1669 Res = Info.getKnownBits(SrcReg); in TEST_F()
1701 Register SrcReg; in TEST_F() local
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H A DKnownBitsVectorTest.cpp37 KnownBits Res = Info.getKnownBits(SrcReg); in TEST_F()
79 KnownBits Res = Info.getKnownBits(SrcReg); in TEST_F()
1050 Register SrcReg; in TEST_F() local
1055 Res = Info.getKnownBits(SrcReg); in TEST_F()
1062 Res = Info.getKnownBits(SrcReg); in TEST_F()
1069 Res = Info.getKnownBits(SrcReg); in TEST_F()
1495 Register SrcReg; in TEST_F() local
1501 Res = Info.getKnownBits(SrcReg); in TEST_F()
1509 Res = Info.getKnownBits(SrcReg); in TEST_F()
1517 Res = Info.getKnownBits(SrcReg); in TEST_F()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp42 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg()
53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
63 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
80 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
84 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && in storeRegToStackSlot()
88 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
98 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h83 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
94 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
131 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
157 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineZExt()
189 LLT SrcTy = MRI.getType(SrcReg); in tryCombineSExt()
202 if (mi_match(SrcReg, MRI, in tryCombineSExt()
533 MRI.replaceRegWith(DstReg, SrcReg); in replaceRegOrBuildCopy()
534 UpdatedDefs.push_back(SrcReg); in replaceRegOrBuildCopy()
589 CurrentBest = SrcReg; in findValueFromConcat()
823 LLT OpTy = MRI.getType(SrcReg); in tryCombineUnmergeValues()
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/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp428 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
480 if (CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
484 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
487 assert(SrcReg < CSKY::R8); in copyPhysReg()
489 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
495 if (CSKY::CARRYRegClass.contains(SrcReg) && in copyPhysReg()
500 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
507 .addReg(SrcReg, RegState::Define) in copyPhysReg()
510 .addReg(SrcReg, getKillRegState(true)); in copyPhysReg()
520 if (CSKY::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
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/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp34 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
47 Register SrcReg = MI->getOperand(1).getReg(); in expandMEMCPY() local
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
126 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
135 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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H A DBPFMISimplifyPatchable.cpp65 MachineInstr &MI, Register &SrcReg, Register &DstReg,
68 Register &SrcReg, const GlobalValue *GVal,
169 MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg, in processCandidate() argument
195 .addReg(SrcReg, 0, BPF::sub_32); in processCandidate()
200 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
204 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument
211 I->setReg(SrcReg); in processDstReg()
285 Register SrcReg = MI.getOperand(1).getReg(); in removeLD() local
287 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD()
310 processCandidate(MRI, MBB, MI, SrcReg, DstReg, GVal, IsAma); in removeLD()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
294 SrcReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
306 if (Hexagon::P0 == SrcReg) { in getDuplexCandidateGroup()
414 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
419 if (DstReg == SrcReg) { in getDuplexCandidateGroup()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSExtWRemoval.cpp318 Register SrcReg = MI->getOperand(1).getReg(); in isSignExtendedW() local
323 if (!SrcReg.isVirtual()) in isSignExtendedW()
325 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in isSignExtendedW()
348 Register SrcReg = MI->getOperand(1).getReg(); in isSignExtendedW() local
349 if (!SrcReg.isVirtual()) in isSignExtendedW()
387 if (!SrcReg.isVirtual()) in isSignExtendedW()
451 if (!SrcReg.isVirtual()) in runOnMachineFunction()
461 Register SrcReg = MI->getOperand(1).getReg(); in runOnMachineFunction() local
462 MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg); in runOnMachineFunction()
492 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
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H A DRISCVInstrInfo.cpp122 return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs; in forwardCopyWillClobberTuple()
135 Register SrcReg = MBBI->getOperand(1).getReg(); in isConvertibleToVMV_V_V() local
224 if (MO.getReg() != SrcReg) in isConvertibleToVMV_V_V()
262 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
268 if (RISCV::VCSRRegClass.contains(SrcReg) && in copyPhysReg()
702 Register SrcReg = RISCV::X0; in movImm() local
720 .addReg(SrcReg, RegState::Kill) in movImm()
726 .addReg(SrcReg, RegState::Kill) in movImm()
727 .addReg(SrcReg, RegState::Kill) in movImm()
732 .addReg(SrcReg, RegState::Kill) in movImm()
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/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp29 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
30 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
32 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
39 if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
41 } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
49 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
53 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, in storeRegToStackSlot() argument
79 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DPHIElimination.cpp443 isImplicitlyDefined(SrcReg, *MRI); in LowerPHINode()
444 assert(Register::isVirtualRegister(SrcReg) && in LowerPHINode()
457 MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg); in LowerPHINode()
464 assert(MRI->use_empty(SrcReg) && in LowerPHINode()
482 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); in LowerPHINode()
512 !LV->isLiveOut(SrcReg, opBlock)) { in LowerPHINode()
532 if (Term->readsRegister(SrcReg)) in LowerPHINode()
546 if (KillInst->readsRegister(SrcReg)) in LowerPHINode()
590 if (Term->readsRegister(SrcReg)) in LowerPHINode()
604 if (KillInst->readsRegister(SrcReg)) in LowerPHINode()
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H A DOptimizePHIs.cpp112 Register SrcReg = MI->getOperand(i).getReg(); in IsSingleValuePHICycle() local
113 if (SrcReg == DstReg) in IsSingleValuePHICycle()
115 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
121 SrcReg = SrcMI->getOperand(1).getReg(); in IsSingleValuePHICycle()
122 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
132 if (SingleValReg != 0 && SingleValReg != SrcReg) in IsSingleValuePHICycle()
134 SingleValReg = SrcReg; in IsSingleValuePHICycle()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
323 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
331 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
335 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
346 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
360 SP::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
363 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
365 SP::ASRRegsRegClass.contains(SrcReg)) { in copyPhysReg()
367 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
379 Register Src = TRI->getSubReg(SrcReg, subRegIdx[i]); in copyPhysReg()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp102 SrcReg = 0; in copyPhysReg()
105 SrcReg = 0; in copyPhysReg()
150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
153 Opc = Mips::MFHI64, SrcReg = 0; in copyPhysReg()
155 Opc = Mips::MFLO64, SrcReg = 0; in copyPhysReg()
179 if (SrcReg) in copyPhysReg()
300 SrcReg = Mips::K0; in storeRegToStack()
303 SrcReg = Mips::K0_64; in storeRegToStack()
306 SrcReg = Mips::K0; in storeRegToStack()
309 SrcReg = Mips::K0_64; in storeRegToStack()
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H A DMipsFastISel.cpp847 .addReg(SrcReg) in emitStore()
907 unsigned SrcReg = 0; in selectStore() local
920 if (SrcReg == 0) in selectStore()
997 Register SrcReg = in selectFPExt() local
1000 if (!SrcReg) in selectFPExt()
1077 if (!SrcReg) in selectFPTrunc()
1113 if (SrcReg == 0) in selectFPToInt()
1592 if (SrcReg == 0) in fastLowerIntrinsicCall()
1752 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1786 if (!SrcReg) in selectTrunc()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp78 Register SrcReg = MI->getOperand(1).getReg(); in visitMBB() local
81 (SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) { in visitMBB()
83 if (SrcReg == SystemZ::CC) in visitMBB()
86 BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg); in visitMBB()
90 else if (SrcReg.isVirtual() && in visitMBB()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp176 Register SrcReg = MI.getOperand(1).getReg(); in matchUCharToFloat() local
177 unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits(); in matchUCharToFloat()
180 return Helper.getKnownBits()->maskedValueIsZero(SrcReg, Mask); in matchUCharToFloat()
192 Register SrcReg = MI.getOperand(1).getReg(); in applyUCharToFloat() local
194 LLT SrcTy = MRI.getType(SrcReg); in applyUCharToFloat()
196 SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0); in applyUCharToFloat()
200 {SrcReg}, MI.getFlags()); in applyUCharToFloat()
203 {SrcReg}, MI.getFlags()); in applyUCharToFloat()
254 Register SrcReg = MI.getOperand(1).getReg(); in matchCvtF32UByteN() local
257 mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg))); in matchCvtF32UByteN()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp261 .addReg(SrcReg) in selectCopy()
276 (SrcReg.isPhysical() && in selectCopy()
285 SrcReg.isPhysical()) { in selectCopy()
719 const LLT SrcTy = MRI.getType(SrcReg); in selectTruncOrPtrToInt()
783 const LLT SrcTy = MRI.getType(SrcReg); in selectZext()
813 Register DefReg = SrcReg; in selectZext()
824 .addReg(SrcReg) in selectZext()
887 .addReg(SrcReg) in selectAnyext()
1185 .addReg(SrcReg, 0, SubIdx); in emitExtractSubreg()
1223 .addReg(SrcReg); in emitInsertSubreg()
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/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp170 Register SrcReg = MI.getOperand(1).getReg(); in runOnMachineFunction() local
178 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
179 assert(canReplaceReg(DstReg, SrcReg, MRI) && in runOnMachineFunction()
182 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
230 Register SrcReg = MI.getOperand(1).getReg(); in runOnMachineFunction() local
232 if (Register::isVirtualRegister(SrcReg) && in runOnMachineFunction()
234 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction()
237 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp659 if (DstReg == SrcReg) in expand()
668 .addReg(SrcReg); in expand()
779 if (DstReg == SrcReg) in expand()
788 .addReg(SrcReg) in expand()
836 if (DstReg == SrcReg) in expandLPMWELPMW()
845 .addReg(SrcReg); in expandLPMWELPMW()
2288 if (SrcReg != DstLoReg) in expand()
2291 .addReg(SrcReg); in expand()
2293 if (SrcReg != DstHiReg) { in expand()
2296 .addReg(SrcReg); in expand()
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/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp634 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
638 else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
643 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
654 if (M68k::DR8RegClass.contains(SrcReg)) { in copyPhysReg()
659 } else if (M68k::XR16RegClass.contains(SrcReg) && in copyPhysReg()
665 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
669 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
670 bool FromSR = SrcReg == M68k::SR; in copyPhysReg()
679 assert(M68k::DR8RegClass.contains(SrcReg) && in copyPhysReg()
687 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
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