182   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr);
183   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
192   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
215   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,  in emitInstStore()  argument
217     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);  in emitInstStore()
806 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr) {  in emitStore()  argument
836     emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());  in emitStore()
847         .addReg(SrcReg)  in emitStore()
907   unsigned SrcReg = 0;  in selectStore()  local
919   SrcReg = getRegForValue(Op0);  in selectStore()
920   if (SrcReg == 0)  in selectStore()
928   if (!emitStore(VT, SrcReg, Addr))  in selectStore()
997   Register SrcReg =  in selectFPExt()  local
1000   if (!SrcReg)  in selectFPExt()
1004   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);  in selectFPExt()
1076   Register SrcReg = getRegForValue(Src);  in selectFPTrunc()  local
1077   if (!SrcReg)  in selectFPTrunc()
1084   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);  in selectFPTrunc()
1112   Register SrcReg = getRegForValue(Src);  in selectFPToInt()  local
1113   if (SrcReg == 0)  in selectFPToInt()
1123   emitInst(Opc, TempReg).addReg(SrcReg);  in selectFPToInt()
1458     unsigned SrcReg = Allocation[ArgNo].Reg;  in fastLowerArguments()  local
1459     Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);  in fastLowerArguments()
1591     Register SrcReg = getRegForValue(II->getOperand(0));  in fastLowerIntrinsicCall()  local
1592     if (SrcReg == 0)  in fastLowerIntrinsicCall()
1599         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);  in fastLowerIntrinsicCall()
1609         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1610         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1619         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);  in fastLowerIntrinsicCall()
1631         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1632         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);  in fastLowerIntrinsicCall()
1636         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);  in fastLowerIntrinsicCall()
1639         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);  in fastLowerIntrinsicCall()
1721     unsigned SrcReg = Reg + VA.getValNo();  in selectRet()  local
1724     if (!MRI.getRegClass(SrcReg)->contains(DestReg))  in selectRet()
1752         SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);  in selectRet()
1753         if (SrcReg == 0)  in selectRet()
1760             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);  in selectRet()
1785   Register SrcReg = getRegForValue(Op);  in selectTrunc()  local
1786   if (!SrcReg)  in selectTrunc()
1791   updateValueMap(I, SrcReg);  in selectTrunc()
1801   Register SrcReg = getRegForValue(Src);  in selectIntExt()  local
1802   if (!SrcReg)  in selectIntExt()
1817   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))  in selectIntExt()
1823 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntSExt32r1()  argument
1837   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);  in emitIntSExt32r1()
1842 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntSExt32r2()  argument
1848     emitInst(Mips::SEB, DestReg).addReg(SrcReg);  in emitIntSExt32r2()
1851     emitInst(Mips::SEH, DestReg).addReg(SrcReg);  in emitIntSExt32r2()
1857 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntSExt()  argument
1862     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);  in emitIntSExt()
1863   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);  in emitIntSExt()
1866 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntZExt()  argument
1884   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);  in emitIntZExt()
1888 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
1898     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);  in emitIntExt()
1899   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);  in emitIntExt()
1902 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
1905   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);  in emitIntExt()