162   Register SrcReg = MI.getOperand(2).getReg();  in expandArith()  local
167   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expandArith()
195   Register SrcReg = MI.getOperand(2).getReg();  in expandLogic()  local
200   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expandLogic()
486   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
492   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
519   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
525   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
652   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
659   if (DstReg == SrcReg)  in expand()
662   Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;  in expand()
663   Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;  in expand()
668                    .addReg(SrcReg);  in expand()
677                    .addReg(SrcReg, getKillRegState(SrcIsKill))  in expand()
700   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
707   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");  in expand()
712           .addReg(SrcReg, RegState::Define)  in expand()
713           .addReg(SrcReg, RegState::Kill);  in expand()
718           .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))  in expand()
719           .addReg(SrcReg, RegState::Kill);  in expand()
733   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
740   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");  in expand()
745           .addReg(SrcReg, RegState::Define)  in expand()
746           .addReg(SrcReg, RegState::Kill);  in expand()
751           .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))  in expand()
752           .addReg(SrcReg, RegState::Kill);  in expand()
767   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
779   if (DstReg == SrcReg)  in expand()
782   Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;  in expand()
783   Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;  in expand()
788                    .addReg(SrcReg)  in expand()
798                    .addReg(SrcReg, getKillRegState(SrcIsKill))  in expand()
821   Register SrcReg = MI.getOperand(1).getReg();  in expandLPMWELPMW()  local
836   if (DstReg == SrcReg)  in expandLPMWELPMW()
839   Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;  in expandLPMWELPMW()
840   Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;  in expandLPMWELPMW()
845                    .addReg(SrcReg);  in expandLPMWELPMW()
854                    .addReg(SrcReg, getKillRegState(SrcIsKill));  in expandLPMWELPMW()
885   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
896                   .addReg(SrcReg, getKillRegState(SrcIsKill));  in expand()
1017   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
1021   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
1064   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
1069   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
1093   Register SrcReg = MI.getOperand(2).getReg();  in expand()  local
1099   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
1101   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");  in expand()
1128   Register SrcReg = MI.getOperand(2).getReg();  in expand()  local
1134   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
1136   assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");  in expand()
1165   Register SrcReg = MI.getOperand(2).getReg();  in expand()  local
1182         .addReg(SrcReg, getKillRegState(SrcIsKill));  in expand()
1191     TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
1286   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
1290   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
1316   Register SrcReg = MI.getOperand(0).getReg();  in expand()  local
1321   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()
2282   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
2288   if (SrcReg != DstLoReg)  in expand()
2291         .addReg(SrcReg);  in expand()
2293   if (SrcReg != DstHiReg) {  in expand()
2296                    .addReg(SrcReg);  in expand()
2297     if (SrcReg != DstLoReg && SrcIsKill)  in expand()
2334   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
2340   if (SrcReg != DstLoReg) {  in expand()
2343         .addReg(SrcReg, getKillRegState(SrcIsKill));  in expand()
2391   Register SrcReg = MI.getOperand(1).getReg();  in expand()  local
2394   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);  in expand()