120 static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,  in forwardCopyWillClobberTuple()  argument
122   return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs;  in forwardCopyWillClobberTuple()
135   Register SrcReg = MBBI->getOperand(1).getReg();  in isConvertibleToVMV_V_V()  local
209         if (!FoundDef && TRI->isSubRegisterEq(MO.getReg(), SrcReg)) {  in isConvertibleToVMV_V_V()
224           if (MO.getReg() != SrcReg)  in isConvertibleToVMV_V_V()
259                                  MCRegister SrcReg, bool KillSrc) const {  in copyPhysReg()  argument
260   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
262         .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
268   if (RISCV::VCSRRegClass.contains(SrcReg) &&  in copyPhysReg()
272       .addImm(RISCVSysReg::lookupSysRegByName(TRI.getName(SrcReg))->Encoding)  in copyPhysReg()
283   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
286   } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
289   } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
292   } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
295   } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
298   } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
301   } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
304   } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
309   } else if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
314   } else if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
319   } else if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
324   } else if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
329   } else if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
334   } else if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
339   } else if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
344   } else if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
349   } else if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
354   } else if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {  in copyPhysReg()
406         MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
419       unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);  in copyPhysReg()
437           MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),  in copyPhysReg()
449         .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
450         .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
456                                          Register SrcReg, bool IsKill, int FI,  in storeRegToStackSlot()  argument
526                    .addReg(SrcReg, getKillRegState(IsKill))  in storeRegToStackSlot()
541         .addReg(SrcReg, getKillRegState(IsKill))  in storeRegToStackSlot()
702   Register SrcReg = RISCV::X0;  in movImm()  local
720           .addReg(SrcReg, RegState::Kill)  in movImm()
726           .addReg(SrcReg, RegState::Kill)  in movImm()
727           .addReg(SrcReg, RegState::Kill)  in movImm()
732           .addReg(SrcReg, RegState::Kill)  in movImm()
739     SrcReg = DstReg;  in movImm()