393                                         Register SrcReg, bool IsKill, int FI,  in storeRegToStackSlot()  argument
428       .addReg(SrcReg, getKillRegState(IsKill))  in storeRegToStackSlot()
479                                 MCRegister SrcReg, bool KillSrc) const {  in copyPhysReg()  argument
480   if (CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
484           .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
487       assert(SrcReg < CSKY::R8);  in copyPhysReg()
489           .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
495   if (CSKY::CARRYRegClass.contains(SrcReg) &&  in copyPhysReg()
500           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
507           .addReg(SrcReg, RegState::Define)  in copyPhysReg()
510           .addReg(SrcReg, getKillRegState(true));  in copyPhysReg()
512           .addReg(SrcReg, RegState::Define | getDeadRegState(KillSrc))  in copyPhysReg()
520   if (CSKY::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
522   else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
524   else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
526   else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
528   else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
530   else if (v2sf && CSKY::sFPR32RegClass.contains(SrcReg) &&  in copyPhysReg()
533   else if (v3sf && CSKY::FPR32RegClass.contains(SrcReg) &&  in copyPhysReg()
536   else if (v2df && CSKY::sFPR64RegClass.contains(SrcReg) &&  in copyPhysReg()
539   else if (v3df && CSKY::FPR64RegClass.contains(SrcReg) &&  in copyPhysReg()
542   else if (v2sf && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
545   else if (v3sf && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
548   else if (v2df && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
551   else if (v3df && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
555     LLVM_DEBUG(dbgs() << "src = " << SrcReg << ", dst = " << DestReg);  in copyPhysReg()
561       .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()