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Searched refs:SRL (Results 1 – 25 of 117) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h36 SRL = 0x27, enumerator
94 case SRL: in lanaiAluCodeToString()
113 .Case("srl", SRL) in stringToLanaiAluCode()
136 case ISD::SRL: in isdToLanaiAluCode()
137 return AluCode::SRL; in isdToLanaiAluCode()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp61 setOperationAction(ISD::SRL, MVT::i32, Custom); in LoongArchTargetLowering()
107 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
125 case ISD::SRL: in LowerOperation()
253 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in lowerShiftLeftParts()
255 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt); in lowerShiftLeftParts()
294 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
303 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
332 case ISD::SRL: in getLoongArchWOpcode()
361 case ISD::SRL: in ReplaceNodeResults()
424 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll45 ; 64: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dshift-09.ll28 ; Check that we use SRLK over SRL where useful.
39 ; Check that we use SRL over SRLK where possible.
H A Dshift-02.ll6 ; Check the low end of the SRL range.
16 ; Check the high end of the defined SRL range.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp643 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
646 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
649 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
738 { ISD::SRL, MVT::v16i8, 2 }, in getArithmeticInstrCost()
741 { ISD::SRL, MVT::v8i16, 2 }, in getArithmeticInstrCost()
744 { ISD::SRL, MVT::v4i32, 2 }, in getArithmeticInstrCost()
747 { ISD::SRL, MVT::v2i64, 2 }, in getArithmeticInstrCost()
751 { ISD::SRL, MVT::v32i8, 4+2 }, in getArithmeticInstrCost()
754 { ISD::SRL, MVT::v16i16, 4+2 }, in getArithmeticInstrCost()
757 { ISD::SRL, MVT::v8i32, 4+2 }, in getArithmeticInstrCost()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dvalid.s147 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
150 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
153 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
156 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1015 case ISD::SRL: { in combineShiftToAVG()
1705 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1714 Opc = ISD::SRL; in SimplifyDemandedBits()
1828 case ISD::SRL: { in SimplifyDemandedBits()
1853 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
2376 case ISD::SRL: in SimplifyDemandedBits()
3343 case ISD::SRL: in SimplifyDemandedVectorElts()
3864 NewShiftOpcode = ISD::SRL; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
3866 case ISD::SRL: in optimizeSetCCByHoistingAndByConstFromLogicalShift()
7383 DAG.getNode(ISD::SRL, dl, DstVT, R, in expandFP_TO_SINT()
[all …]
H A DLegalizeIntegerTypes.cpp100 case ISD::SRL: in PromoteIntegerResult()
523 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
903 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
1676 case ISD::SRL: in PromoteIntegerOperand()
2635 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
2639 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
2718 case ISD::SRL: in ExpandShiftWithKnownAmountBit()
2743 case ISD::SRL: in ExpandShiftWithKnownAmountBit()
2811 case ISD::SRL: in ExpandShiftWithUnknownAmountBit()
4168 } else if (N->getOpcode() == ISD::SRL) { in ExpandIntRes_Shift()
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H A DDAGCombiner.cpp1438 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1854 case ISD::SRL: in combine()
5956 InnerShift = ISD::SRL; in unfoldExtremeBitClearingToShifts()
6686 if (Opc0 != ISD::SRL) in isBSwapHWordElement()
9472 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
12816 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
12817 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; in reduceLoadWidth() local
12823 if (!SRL.hasOneUse()) in reduceLoadWidth()
12877 N0 = SRL.getOperand(0); in reduceLoadWidth()
13058 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dvalid.s188 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
191 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
194 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
197 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dbitwise.mir293 ; MIPS32: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY]], 1
294 ; MIPS32: $v0 = COPY [[SRL]]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dvalid.s251 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
254 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
257 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
260 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32/
H A Dvalid.s249 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
252 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
255 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
258 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dload-shift-combine.ll5 ; load. Later the pre-increment load is combined with a subsequent SRL to
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp85 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
88 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
288 case ISD::SRL: in LowerShifts()
326 case ISD::SRL: in LowerShifts()
344 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
356 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { in LowerShifts()
401 case ISD::SRL: in LowerShifts()
418 case ISD::SRL: in LowerShifts()
444 case ISD::SRL: in LowerShifts()
845 case ISD::SRL: in LowerOperation()
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s298 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
301 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
304 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
307 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s297 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
300 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
303 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
306 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s297 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
300 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
303 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
306 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s330 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
333 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
336 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
339 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s311 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
314 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
317 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
320 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s312 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
315 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
318 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
321 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def103 ADD_BINARY_VVP_OP(VVP_SRL,VP_LSHR,SRL) REGISTER_PACKED(VVP_SRL)
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp787 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
1196 N->getOperand(0).getOpcode() == ISD::SRL) || in shouldFoldConstantShiftPairToMask()
1197 (N->getOpcode() == ISD::SRL && in shouldFoldConstantShiftPairToMask()
2406 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
2407 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2453 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
2487 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
2594 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, in lowerShiftLeftParts()
2637 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, in lowerShiftRightParts()
2738 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in lowerLOAD() local
[all …]

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