359     { ISD::SRL,  MVT::v64i8,   2 }, // psrlw + pand.  in getArithmeticInstrCost()
376     { ISD::SRL,  MVT::v64i8,   4 }, // psrlw + pand.  in getArithmeticInstrCost()
394     { ISD::SRL,  MVT::v32i8,   2 }, // psrlw + pand.  in getArithmeticInstrCost()
414     { ISD::SRL,  MVT::v16i8,     2 }, // psrlw + pand.  in getArithmeticInstrCost()
418     { ISD::SRL,  MVT::v32i8,   4+2 }, // 2*(psrlw + pand) + split.  in getArithmeticInstrCost()
549     { ISD::SRL,   MVT::v16i8,      4 }, // extend/vpsrlvw/pack sequence.  in getArithmeticInstrCost()
552     { ISD::SRL,   MVT::v32i8,      4 }, // extend/vpsrlvw/pack sequence.  in getArithmeticInstrCost()
555     { ISD::SRL,   MVT::v64i8,      7 }, // extend/vpsrlvw/pack sequence.  in getArithmeticInstrCost()
559     { ISD::SRL,   MVT::v8i16,      1 }, // vpsrlvw  in getArithmeticInstrCost()
562     { ISD::SRL,   MVT::v16i16,     1 }, // vpsrlvw  in getArithmeticInstrCost()
565     { ISD::SRL,   MVT::v32i16,     1 }, // vpsrlvw  in getArithmeticInstrCost()
576     { ISD::SRL,  MVT::v16i16, 1 }, // psrlw.  in getArithmeticInstrCost()
579     { ISD::SRL,  MVT::v32i16, 2 }, // 2*psrlw.  in getArithmeticInstrCost()
583     { ISD::SRL,  MVT::v8i32,  1 }, // psrld  in getArithmeticInstrCost()
586     { ISD::SRL,  MVT::v4i64,  1 }, // psrlq  in getArithmeticInstrCost()
603     { ISD::SRL,  MVT::v8i16,  1 }, // psrlw.  in getArithmeticInstrCost()
604     { ISD::SRL,  MVT::v4i32,  1 }, // psrld.  in getArithmeticInstrCost()
605     { ISD::SRL,  MVT::v2i64,  1 }, // psrlq.  in getArithmeticInstrCost()
632     { ISD::SRL,   MVT::v64i8,     11 }, // vpblendvb sequence.  in getArithmeticInstrCost()
643     { ISD::SRL,     MVT::v4i32,      1 },  in getArithmeticInstrCost()
646     { ISD::SRL,     MVT::v8i32,      1 },  in getArithmeticInstrCost()
649     { ISD::SRL,     MVT::v16i32,     1 },  in getArithmeticInstrCost()
653     { ISD::SRL,     MVT::v2i64,      1 },  in getArithmeticInstrCost()
655     { ISD::SRL,     MVT::v4i64,      1 },  in getArithmeticInstrCost()
657     { ISD::SRL,     MVT::v8i64,      1 },  in getArithmeticInstrCost()
696     { ISD::SRL,     MVT::v4i32,    2 }, // vpsrlvd (Haswell from agner.org)  in getArithmeticInstrCost()
699     { ISD::SRL,     MVT::v8i32,    2 }, // vpsrlvd (Haswell from agner.org)  in getArithmeticInstrCost()
702     { ISD::SRL,     MVT::v2i64,    1 }, // vpsrlvq (Haswell from agner.org)  in getArithmeticInstrCost()
704     { ISD::SRL,     MVT::v4i64,    1 }, // vpsrlvq (Haswell from agner.org)  in getArithmeticInstrCost()
738     { ISD::SRL,     MVT::v16i8,    2 },  in getArithmeticInstrCost()
741     { ISD::SRL,     MVT::v8i16,    2 },  in getArithmeticInstrCost()
744     { ISD::SRL,     MVT::v4i32,    2 },  in getArithmeticInstrCost()
747     { ISD::SRL,     MVT::v2i64,    2 },  in getArithmeticInstrCost()
751     { ISD::SRL,     MVT::v32i8,  4+2 },  in getArithmeticInstrCost()
754     { ISD::SRL,     MVT::v16i16, 4+2 },  in getArithmeticInstrCost()
757     { ISD::SRL,     MVT::v8i32,  4+2 },  in getArithmeticInstrCost()
760     { ISD::SRL,     MVT::v4i64,  4+2 },  in getArithmeticInstrCost()
769     if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) &&  in getArithmeticInstrCost()
784     { ISD::SRL,  MVT::v16i16, 2+2 }, // 2*psrlw + split.  in getArithmeticInstrCost()
785     { ISD::SRL,  MVT::v8i32,  2+2 }, // 2*psrld + split.  in getArithmeticInstrCost()
786     { ISD::SRL,  MVT::v4i64,  2+2 }, // 2*psrlq + split.  in getArithmeticInstrCost()
825     { ISD::SRL,  MVT::v16i8,      6 }, // vpblendvb sequence.  in getArithmeticInstrCost()
826     { ISD::SRL,  MVT::v32i8,      6 }, // vpblendvb sequence.  in getArithmeticInstrCost()
827     { ISD::SRL,  MVT::v64i8,     12 }, // 2*vpblendvb sequence.  in getArithmeticInstrCost()
828     { ISD::SRL,  MVT::v8i16,      5 }, // extend/vpsrlvd/pack sequence.  in getArithmeticInstrCost()
829     { ISD::SRL,  MVT::v16i16,     7 }, // extend/vpsrlvd/pack sequence.  in getArithmeticInstrCost()
830     { ISD::SRL,  MVT::v32i16,    14 }, // 2*extend/vpsrlvd/pack sequence.  in getArithmeticInstrCost()
903     { ISD::SRL,     MVT::v32i8,     23 }, // pblendvb sequence + split.  in getArithmeticInstrCost()
904     { ISD::SRL,     MVT::v16i16,    28 }, // pblendvb sequence + split.  in getArithmeticInstrCost()
905     { ISD::SRL,     MVT::v4i32,      6 }, // Shift each lane + blend.  in getArithmeticInstrCost()
906     { ISD::SRL,     MVT::v8i32,     14 }, // Shift each lane + blend + split.  in getArithmeticInstrCost()
907     { ISD::SRL,     MVT::v2i64,      2 }, // Shift each lane + blend.  in getArithmeticInstrCost()
908     { ISD::SRL,     MVT::v4i64,      6 }, // Shift each lane + blend + split.  in getArithmeticInstrCost()
969     { ISD::SRL,  MVT::v16i8,      11 }, // pblendvb sequence.  in getArithmeticInstrCost()
970     { ISD::SRL,  MVT::v8i16,      13 }, // pblendvb sequence.  in getArithmeticInstrCost()
971     { ISD::SRL,  MVT::v4i32,      16 }, // Shift each lane + blend.  in getArithmeticInstrCost()
991     { ISD::SRL,  MVT::v16i8,      14 }, // cmpgtb sequence.  in getArithmeticInstrCost()
992     { ISD::SRL,  MVT::v8i16,      16 }, // cmpgtw sequence.  in getArithmeticInstrCost()
993     { ISD::SRL,  MVT::v4i32,      12 }, // Shift each lane + blend.  in getArithmeticInstrCost()
994     { ISD::SRL,  MVT::v2i64,       4 }, // splat+shuffle sequence.  in getArithmeticInstrCost()