Lines Matching refs:SRL
1438 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1721 case ISD::SRL: return visitSRL(N); in visit()
1854 case ISD::SRL: in combine()
2220 case ISD::SRL: // X u>> 0 --> X in foldSelectWithIdentityConstant()
2375 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2397 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit()
3462 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3465 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
3733 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
4411 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike()
4517 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitUDIVLike()
4533 return DAG.getNode(ISD::SRL, DL, VT, N0, Add); in visitUDIVLike()
4603 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && in visitREM()
4701 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
4750 DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) { in visitMULHU()
4757 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitMULHU()
4771 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
4812 return DAG.getNode(ISD::SRL, DL, VT, N0, DAG.getConstant(1, DL, VT)); in visitAVG()
4901 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
4951 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
5312 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL || in hoistLogicOpWithSameOpcodeHands()
5566 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
5601 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in visitANDLike()
5621 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
5639 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK); in visitANDLike()
5956 InnerShift = ISD::SRL; in unfoldExtremeBitClearingToShifts()
5957 else if (OuterShift == ISD::SRL) in unfoldExtremeBitClearingToShifts()
6022 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6112 !(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL || in foldLogicOfShifts()
6533 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
6560 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
6562 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
6628 Res = DAG.getNode(ISD::SRL, DL, VT, Res, in MatchBSwapHWordLow()
6646 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
6651 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
6672 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { in isBSwapHWordElement()
6686 if (Opc0 != ISD::SRL) in isBSwapHWordElement()
6731 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
6767 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
6850 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt)); in MatchBSwapHWord()
6942 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
7131 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
7166 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) in extractShiftForRotate()
7180 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
7205 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
7206 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
7462 if (IsBinOpImm(N1, ISD::SRL, 1) && in MatchFunnelPosNeg()
7577 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) in MatchRotate()
7598 SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt); in MatchRotate()
7647 SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt); in MatchRotate()
7988 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
8737 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
8993 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
9015 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { in visitSHL()
9049 if (N0.getOpcode() == ISD::SRL && in visitSHL()
9059 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, Diff); in visitSHL()
9060 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); in visitSHL()
9142 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
9331 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, in visitSRA()
9398 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
9425 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); in visitSRA()
9454 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, {N0, N1})) in visitSRL()
9472 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
9493 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum); in visitSRL()
9498 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
9514 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL()
9524 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL()
9554 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N01); in visitSRL()
9566 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N1); in visitSRL()
9567 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); in visitSRL()
9581 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
9584 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
9601 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); in visitSRL()
9629 Op = DAG.getNode(ISD::SRL, DL, VT, Op, in visitSRL()
9645 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1); in visitSRL()
9737 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, in visitFunnelShift()
9792 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, N2); in visitFunnelShift()
9952 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitBSWAP()
9958 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; in visitBSWAP()
11603 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
11839 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
12449 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
12763 } else if (Opc == ISD::SRL || Opc == ISD::SRA) { in reduceLoadWidth()
12781 ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD; in reduceLoadWidth()
12816 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
12817 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; in reduceLoadWidth() local
12823 if (!SRL.hasOneUse()) in reduceLoadWidth()
12828 auto *LN = dyn_cast<LoadSDNode>(SRL.getOperand(0)); in reduceLoadWidth()
12829 auto *SRL1C = dyn_cast<ConstantSDNode>(SRL.getOperand(1)); in reduceLoadWidth()
12863 SDNode *Mask = *(SRL->use_begin()); in reduceLoadWidth()
12864 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && in reduceLoadWidth()
12872 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) in reduceLoadWidth()
12877 N0 = SRL.getOperand(0); in reduceLoadWidth()
13058 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
13763 X = DAG.getNode(ISD::SRL, DL, in visitBITCAST()
16048 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
16051 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
17384 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
17560 IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal, in ShrinkLoadReplaceStoreWithStore()
20228 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
23920 SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt); in foldSelectCCToShiftAnd()