Lines Matching refs:SRL
61 setOperationAction(ISD::SRL, MVT::i32, Custom); in LoongArchTargetLowering()
107 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
125 case ISD::SRL: in LowerOperation()
253 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in lowerShiftLeftParts()
255 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt); in lowerShiftLeftParts()
294 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
303 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
332 case ISD::SRL: in getLoongArchWOpcode()
361 case ISD::SRL: in ReplaceNodeResults()
424 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
584 DAG.getNode(ISD::SRL, DL, N1->getValueType(0), N1, in performORCombine()
707 DAG.getNode(ISD::SRL, DL, N1->getValueType(0), in performORCombine()
734 case ISD::SRL: in PerformDAGCombine()