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Searched refs:ResultReg (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1201 if (ResultReg) in emitAddSub()
1532 if (ResultReg) in emitAdd_ri_()
1589 if (ResultReg) in emitLogicalOp()
1636 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp()
1681 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp_ri()
1723 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp_rs()
1889 if (!ResultReg) in selectAddSub()
3113 CLI.ResultReg = ResultReg; in finishCall()
4019 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLSL_rr()
4122 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLSR_rr()
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H A DAArch64InstrInfo.cpp5465 Register ResultReg = Root.getOperand(0).getReg(); in genFusedMultiply() local
5482 if (Register::isVirtualRegister(ResultReg)) in genFusedMultiply()
5483 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
5542 Register ResultReg = Root.getOperand(0).getReg(); in genIndexedMultiply() local
5545 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MulOpc), ResultReg) in genIndexedMultiply()
5655 Register ResultReg = Root.getOperand(0).getReg(); in genMaddR() local
5661 if (Register::isVirtualRegister(ResultReg)) in genMaddR()
5662 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
5671 BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg) in genMaddR()
5694 Register ResultReg = Root.getOperand(0).getReg(); in genSubAdd2SubSub() local
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp708 ResultReg = RR; in X86FastEmitExtend()
1461 if (!ResultReg) in X86SelectCmp()
1473 if (ResultReg) { in X86SelectCmp()
1550 ResultReg = fastEmitZExtFromI1(MVT::i8, ResultReg); in X86SelectZExt()
2016 if (!ResultReg) { in X86SelectDivRem()
2541 if (!ResultReg) in X86SelectTrunc()
2953 if (!ResultReg) in fastLowerIntrinsicCall()
3264 ResultReg = fastEmit_ri(VT, VT, ISD::AND, ResultReg, 1); in fastLowerCall()
3272 if (!ResultReg) in fastLowerCall()
3574 CLI.ResultReg = ResultReg; in fastLowerCall()
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H A DX86InstructionSelector.cpp985 Register ResultReg = I.getOperand(0).getReg(); in selectFCmp() local
987 ResultReg, in selectFCmp()
988 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
1002 TII.get(SETFOpc[2]), ResultReg) in selectFCmp()
1029 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC); in selectFCmp()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp325 if (!ResultReg) in emitLogicalOp()
329 return ResultReg; in emitLogicalOp()
345 return ResultReg; in fastMaterializeAlloca()
366 return ResultReg; in materialize32BitInt()
369 return ResultReg; in materialize32BitInt()
381 return ResultReg; in materialize32BitInt()
876 if (!ResultReg) in selectLogicalOp()
1292 if (!ResultReg) in finishCall()
1299 CLI.ResultReg = ResultReg; in finishCall()
1941 if (!ResultReg) in selectDivRem()
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp512 if (!ResultReg) in selectBinaryOp()
527 if (!ResultReg) in selectBinaryOp()
1357 if (!ResultReg) in selectIntrinsicCall()
1401 if (!ResultReg) in selectCast()
1430 if (!ResultReg) in selectBitCast()
1609 if (ResultReg) { in selectFNeg()
1635 if (!ResultReg) in selectFNeg()
1881 if (ResultReg) in fastEmit_ri_()
1923 return ResultReg; in fastEmitInst_()
1943 return ResultReg; in fastEmitInst_r()
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp592 ResultReg) in copyValue()
594 return ResultReg; in copyValue()
602 Register ResultReg = in fastMaterializeAlloca() local
609 return ResultReg; in fastMaterializeAlloca()
621 Register ResultReg = in fastMaterializeConstant() local
628 return ResultReg; in fastMaterializeConstant()
774 unsigned ResultReg; in selectCall() local
1083 updateValueMap(ICmp, ResultReg); in selectICmp()
1146 ResultReg = notValue(ResultReg); in selectFCmp()
1148 updateValueMap(FCmp, ResultReg); in selectFCmp()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp315 return ResultReg; in fastEmitInst_r()
342 return ResultReg; in fastEmitInst_rr()
367 return ResultReg; in fastEmitInst_ri()
386 return ResultReg; in fastEmitInst_i()
492 if (ResultReg) in ARMMaterializeInt()
493 return ResultReg; in ARMMaterializeInt()
515 return ResultReg; in ARMMaterializeInt()
659 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
665 return ResultReg; in fastMaterializeAlloca()
1033 Register ResultReg; in SelectLoad() local
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H A DARMInstructionSelector.cpp688 auto ResultReg = MIB.getReg(0); in selectGlobal() local
696 .addDef(ResultReg) in selectGlobal()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp465 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
521 if (ResultReg == 0) in PPCEmitLoad()
611 Register ResultReg = 0; in SelectLoad() local
1053 Register ResultReg = 0; in PPCMoveToFPReg() local
1057 return ResultReg; in PPCMoveToFPReg()
1178 Register ResultReg = 0; in PPCMoveToIntReg() local
1182 return ResultReg; in PPCMoveToIntReg()
1542 CLI.ResultReg = ResultReg; in finishCall()
2146 return ResultReg; in PPCMaterialize32BitInt()
2199 return ResultReg; in PPCMaterialize64BitInt()
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H A DPPCRegisterInfo.cpp566 Register ResultReg; in getRegAllocationHints() local
570 ResultReg = ResultOp->getReg(); in getRegAllocationHints()
571 if (Register::isVirtualRegister(ResultReg) && in getRegAllocationHints()
572 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && in getRegAllocationHints()
573 VRM->hasPhys(ResultReg)) { in getRegAllocationHints()
574 Register UACCPhys = VRM->getPhys(ResultReg); in getRegAllocationHints()
584 ResultReg = ResultOp->getReg(); in getRegAllocationHints()
585 if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && in getRegAllocationHints()
586 VRM->hasPhys(ResultReg)) { in getRegAllocationHints()
587 Register ACCPhys = VRM->getPhys(ResultReg); in getRegAllocationHints()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp6470 MRI.replaceRegWith(OldDstReg, ResultReg); in moveScalarAddSub()
6551 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerSelect()
6553 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerSelect()
6579 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerScalarAbs()
6580 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerScalarAbs()
6971 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBCNT()
6975 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in splitScalar64BitBCNT()
7016 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBFE()
7035 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBFE()
7036 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in splitScalar64BitBFE()
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H A DSIRegisterInfo.cpp2247 Register ResultReg = IsCopy ? MI->getOperand(0).getReg() in eliminateFrameIndex() local
2255 auto Shift = BuildMI(*MBB, MI, DL, TII->get(OpCode), ResultReg) in eliminateFrameIndex()
2266 .addReg(ResultReg); in eliminateFrameIndex()
2267 ResultReg = NewDest; in eliminateFrameIndex()
2272 if ((MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) != in eliminateFrameIndex()
2275 Register ScaledReg = ResultReg; in eliminateFrameIndex()
2328 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg) in eliminateFrameIndex()
2331 ResultReg = ScaledReg; in eliminateFrameIndex()
2349 FIOp.ChangeToRegister(ResultReg, false, false, true); in eliminateFrameIndex()
H A DSIISelLowering.cpp3588 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
3606 .addReg(ResultReg) in emitLoadM0FromVGPRLoop()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DFastISel.h90 Register ResultReg; member
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp732 for (unsigned ResultReg : ResultRegs) in buildIntrinsic() local
733 MIB.addDef(ResultReg); in buildIntrinsic()
H A DLegalizerHelper.cpp1519 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); in widenScalarMergeValues() local
1534 MIRBuilder.buildOr(NextResult, ResultReg, Shl); in widenScalarMergeValues()
1535 ResultReg = NextResult; in widenScalarMergeValues()
1539 MIRBuilder.buildTrunc(DstReg, ResultReg); in widenScalarMergeValues()
1541 MIRBuilder.buildIntToPtr(DstReg, ResultReg); in widenScalarMergeValues()
6493 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); in lowerMergeValues() local
6506 MIRBuilder.buildOr(NextResult, ResultReg, Shl); in lowerMergeValues()
6507 ResultReg = NextResult; in lowerMergeValues()
6517 MIRBuilder.buildIntToPtr(DstReg, ResultReg); in lowerMergeValues()