Lines Matching refs:ResultReg
190 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
299 Register ResultReg = createResultReg(RC); in fastEmitInst_r() local
307 ResultReg).addReg(Op0)); in fastEmitInst_r()
312 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
315 return ResultReg; in fastEmitInst_r()
321 Register ResultReg = createResultReg(RC); in fastEmitInst_rr() local
331 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
339 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
342 return ResultReg; in fastEmitInst_rr()
348 Register ResultReg = createResultReg(RC); in fastEmitInst_ri() local
356 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_ri()
364 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_ri()
367 return ResultReg; in fastEmitInst_ri()
373 Register ResultReg = createResultReg(RC); in fastEmitInst_i() local
378 ResultReg).addImm(Imm)); in fastEmitInst_i()
383 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_i()
386 return ResultReg; in fastEmitInst_i()
488 unsigned ResultReg = 0; in ARMMaterializeInt() local
490 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in ARMMaterializeInt()
492 if (ResultReg) in ARMMaterializeInt()
493 return ResultReg; in ARMMaterializeInt()
502 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
505 TII.get(ARM::t2LDRpci), ResultReg) in ARMMaterializeInt()
509 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
511 TII.get(ARM::LDRcp), ResultReg) in ARMMaterializeInt()
515 return ResultReg; in ARMMaterializeInt()
658 Register ResultReg = createResultReg(RC); in fastMaterializeAlloca() local
659 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
662 TII.get(Opc), ResultReg) in fastMaterializeAlloca()
665 return ResultReg; in fastMaterializeAlloca()
833 Register ResultReg = createResultReg(RC); in ARMSimplifyAddress() local
836 TII.get(Opc), ResultReg) in ARMSimplifyAddress()
839 Addr.Base.Reg = ResultReg; in ARMSimplifyAddress()
898 bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, in ARMEmitLoad() argument
986 ResultReg = createResultReg(RC); in ARMEmitLoad()
987 assert(ResultReg > 255 && "Expected an allocated virtual register."); in ARMEmitLoad()
989 TII.get(Opc), ResultReg); in ARMEmitLoad()
998 .addReg(ResultReg)); in ARMEmitLoad()
999 ResultReg = MoveReg; in ARMEmitLoad()
1033 Register ResultReg; in SelectLoad() local
1034 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlign())) in SelectLoad()
1036 updateValueMap(I, ResultReg); in SelectLoad()
1562 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP() local
1564 TII.get(Opc), ResultReg).addReg(FP)); in SelectIToFP()
1565 updateValueMap(I, ResultReg); in SelectIToFP()
1589 Register ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in SelectFPToI() local
1591 TII.get(Opc), ResultReg).addReg(Op)); in SelectFPToI()
1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
1655 Register ResultReg = createResultReg(RC); in SelectSelect() local
1660 ResultReg) in SelectSelect()
1668 ResultReg) in SelectSelect()
1674 updateValueMap(I, ResultReg); in SelectSelect()
1766 Register ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectBinaryIntOp() local
1770 TII.get(Opc), ResultReg) in SelectBinaryIntOp()
1772 updateValueMap(I, ResultReg); in SelectBinaryIntOp()
1815 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp() local
1817 TII.get(Opc), ResultReg) in SelectBinaryFPOp()
1819 updateValueMap(I, ResultReg); in SelectBinaryFPOp()
2042 Register ResultReg = createResultReg(DstRC); in FinishCall() local
2044 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
2052 updateValueMap(I, ResultReg); in FinishCall()
2063 Register ResultReg = createResultReg(DstRC); in FinishCall() local
2066 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2070 updateValueMap(I, ResultReg); in FinishCall()
2469 Register ResultReg; in ARMTryEmitSmallMemCpy() local
2470 RV = ARMEmitLoad(VT, ResultReg, Src); in ARMTryEmitSmallMemCpy()
2472 RV = ARMEmitStore(VT, ResultReg, Dest); in ARMTryEmitSmallMemCpy()
2703 unsigned ResultReg; in ARMEmitIntExt() local
2719 ResultReg = createResultReg(RC); in ARMEmitIntExt()
2726 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg); in ARMEmitIntExt()
2736 SrcReg = ResultReg; in ARMEmitIntExt()
2739 return ResultReg; in ARMEmitIntExt()
2761 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); in SelectIntExt() local
2762 if (ResultReg == 0) return false; in SelectIntExt()
2763 updateValueMap(I, ResultReg); in SelectIntExt()
2803 Register ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectShift() local
2804 if(ResultReg == 0) return false; in SelectShift()
2807 TII.get(Opc), ResultReg) in SelectShift()
2818 updateValueMap(I, ResultReg); in SelectShift()
2944 Register ResultReg = MI->getOperand(0).getReg(); in tryToFoldLoadIntoMI() local
2945 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlign(), isZExt, false)) in tryToFoldLoadIntoMI()
3067 Register ResultReg = createResultReg(RC); in fastLowerArguments() local
3070 ResultReg).addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
3071 updateValueMap(&Arg, ResultReg); in fastLowerArguments()