181   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr);
324   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLogicalOp()  local
325   if (!ResultReg)  in emitLogicalOp()
328   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);  in emitLogicalOp()
329   return ResultReg;  in emitLogicalOp()
340     Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in fastMaterializeAlloca()  local
342             ResultReg)  in fastMaterializeAlloca()
345     return ResultReg;  in fastMaterializeAlloca()
361   Register ResultReg = createResultReg(RC);  in materialize32BitInt()  local
365     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);  in materialize32BitInt()
366     return ResultReg;  in materialize32BitInt()
368     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);  in materialize32BitInt()
369     return ResultReg;  in materialize32BitInt()
377     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);  in materialize32BitInt()
379     emitInst(Mips::LUi, ResultReg).addImm(Hi);  in materialize32BitInt()
381   return ResultReg;  in materialize32BitInt()
633 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {  in emitCmp()  argument
650     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
656     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);  in emitCmp()
660     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
663     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
668     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
674     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
678     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
681     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
686     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
692     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
742     emitInst(CondMovOpc, ResultReg)  in emitCmp()
752 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr) {  in emitLoad()  argument
759     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
763     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
767     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
773     ResultReg = createResultReg(&Mips::FGR32RegClass);  in emitLoad()
779     ResultReg = createResultReg(&Mips::AFGR64RegClass);  in emitLoad()
787     emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());  in emitLoad()
797     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in emitLoad()
861   unsigned ResultReg;  in selectLogicalOp()  local
866     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
869     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
872     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
876   if (!ResultReg)  in selectLogicalOp()
879   updateValueMap(I, ResultReg);  in selectLogicalOp()
898   unsigned ResultReg;  in selectLoad()  local
899   if (!emitLoad(VT, ResultReg, Addr))  in selectLoad()
901   updateValueMap(I, ResultReg);  in selectLoad()
979   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectCmp()  local
980   if (!emitCmp(ResultReg, CI))  in selectCmp()
982   updateValueMap(I, ResultReg);  in selectCmp()
1052   Register ResultReg = createResultReg(RC);  in selectSelect()  local
1055   if (!ResultReg || !TempReg)  in selectSelect()
1059   emitInst(CondMovOpc, ResultReg)  in selectSelect()
1061   updateValueMap(I, ResultReg);  in selectSelect()
1291     Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));  in finishCall()  local
1292     if (!ResultReg)  in finishCall()
1296             ResultReg).addReg(RVLocs[0].getLocReg());  in finishCall()
1299     CLI.ResultReg = ResultReg;  in finishCall()
1463     Register ResultReg = createResultReg(Allocation[ArgNo].RC);  in fastLowerArguments()  local
1465             TII.get(TargetOpcode::COPY), ResultReg)  in fastLowerArguments()
1467     updateValueMap(&FormalArg, ResultReg);  in fastLowerArguments()
1815   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectIntExt()  local
1817   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))  in selectIntExt()
1819   updateValueMap(I, ResultReg);  in selectIntExt()
1940   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectDivRem()  local
1941   if (!ResultReg)  in selectDivRem()
1947   emitInst(MFOpc, ResultReg);  in selectDivRem()
1949   updateValueMap(I, ResultReg);  in selectDivRem()
1959   Register ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()  local
1960   if (!ResultReg)  in selectShift()
2000     emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);  in selectShift()
2001     updateValueMap(I, ResultReg);  in selectShift()
2023   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);  in selectShift()
2024   updateValueMap(I, ResultReg);  in selectShift()
2126     Register ResultReg = createResultReg(RC);  in fastEmitInst_rr()  local
2130     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in fastEmitInst_rr()
2135     return ResultReg;  in fastEmitInst_rr()