358     Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);  in fastMaterializeAlloca()  local
360             ResultReg)  in fastMaterializeAlloca()
364     return ResultReg;  in fastMaterializeAlloca()
381   Register ResultReg = createResultReg(RC);  in materializeInt()  local
383           ResultReg).addReg(ZeroReg, getKillRegState(true));  in materializeInt()
384   return ResultReg;  in materializeInt()
417     Register ResultReg = createResultReg(TLI.getRegClassFor(VT));  in materializeFP()  local
419             TII.get(TargetOpcode::COPY), ResultReg)  in materializeFP()
422     return ResultReg;  in materializeFP()
435   Register ResultReg = createResultReg(TLI.getRegClassFor(VT));  in materializeFP()  local
436   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in materializeFP()
439   return ResultReg;  in materializeFP()
459   unsigned ResultReg;  in materializeGV()  local
469       ResultReg = createResultReg(&AArch64::GPR32RegClass);  in materializeGV()
472       ResultReg = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
476             ResultReg)  in materializeGV()
481       return ResultReg;  in materializeGV()
490         .addReg(ResultReg, RegState::Kill)  in materializeGV()
499     ResultReg = createResultReg(&AArch64::GPR64spRegClass);  in materializeGV()
501             ResultReg)  in materializeGV()
507   return ResultReg;  in materializeGV()
1037     Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);  in simplifyAddress()  local
1039             ResultReg)  in simplifyAddress()
1044     Addr.setReg(ResultReg);  in simplifyAddress()
1048     unsigned ResultReg = 0;  in simplifyAddress()  local
1052         ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),  in simplifyAddress()
1056         ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),  in simplifyAddress()
1061         ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),  in simplifyAddress()
1064         ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),  in simplifyAddress()
1067         ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),  in simplifyAddress()
1070     if (!ResultReg)  in simplifyAddress()
1073     Addr.setReg(ResultReg);  in simplifyAddress()
1082     unsigned ResultReg;  in simplifyAddress()  local
1085       ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), Offset);  in simplifyAddress()
1087       ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);  in simplifyAddress()
1089     if (!ResultReg)  in simplifyAddress()
1091     Addr.setReg(ResultReg);  in simplifyAddress()
1188   unsigned ResultReg = 0;  in emitAddSub()  local
1192       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,  in emitAddSub()
1195       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,  in emitAddSub()
1199       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);  in emitAddSub()
1201   if (ResultReg)  in emitAddSub()
1202     return ResultReg;  in emitAddSub()
1238       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,  in emitAddSub()
1240       if (ResultReg)  in emitAddSub()
1241         return ResultReg;  in emitAddSub()
1261           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,  in emitAddSub()
1263           if (ResultReg)  in emitAddSub()
1264             return ResultReg;  in emitAddSub()
1302   unsigned ResultReg;  in emitAddSub_rr()  local
1304     ResultReg = createResultReg(RC);  in emitAddSub_rr()
1306     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_rr()
1311   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_rr()
1314   return ResultReg;  in emitAddSub_rr()
1347   unsigned ResultReg;  in emitAddSub_ri()  local
1349     ResultReg = createResultReg(RC);  in emitAddSub_ri()
1351     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_ri()
1355   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_ri()
1359   return ResultReg;  in emitAddSub_ri()
1388   unsigned ResultReg;  in emitAddSub_rs()  local
1390     ResultReg = createResultReg(RC);  in emitAddSub_rs()
1392     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_rs()
1397   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_rs()
1401   return ResultReg;  in emitAddSub_rs()
1432   unsigned ResultReg;  in emitAddSub_rx()  local
1434     ResultReg = createResultReg(RC);  in emitAddSub_rx()
1436     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_rx()
1441   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_rx()
1445   return ResultReg;  in emitAddSub_rx()
1526   unsigned ResultReg;  in emitAdd_ri_()  local
1528     ResultReg = emitAddSub_ri(false, VT, Op0, -Imm);  in emitAdd_ri_()
1530     ResultReg = emitAddSub_ri(true, VT, Op0, Imm);  in emitAdd_ri_()
1532   if (ResultReg)  in emitAdd_ri_()
1533     return ResultReg;  in emitAdd_ri_()
1539   ResultReg = emitAddSub_rr(true, VT, Op0, CReg);  in emitAdd_ri_()
1540   return ResultReg;  in emitAdd_ri_()
1584   unsigned ResultReg = 0;  in emitLogicalOp()  local
1587     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);  in emitLogicalOp()
1589   if (ResultReg)  in emitLogicalOp()
1590     return ResultReg;  in emitLogicalOp()
1608       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1609       if (ResultReg)  in emitLogicalOp()
1610         return ResultReg;  in emitLogicalOp()
1622         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1623         if (ResultReg)  in emitLogicalOp()
1624           return ResultReg;  in emitLogicalOp()
1633   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);  in emitLogicalOp()
1636     ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);  in emitLogicalOp()
1638   return ResultReg;  in emitLogicalOp()
1676   Register ResultReg =  in emitLogicalOp_ri()  local
1681     ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);  in emitLogicalOp_ri()
1683   return ResultReg;  in emitLogicalOp_ri()
1718   Register ResultReg =  in emitLogicalOp_rs()  local
1723     ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);  in emitLogicalOp_rs()
1725   return ResultReg;  in emitLogicalOp_rs()
1844   Register ResultReg = createResultReg(RC);  in emitLoad()  local
1846                                     TII.get(Opc), ResultReg);  in emitLoad()
1851     unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, 1);  in emitLoad()
1853     ResultReg = ANDReg;  in emitLoad()
1863         .addReg(ResultReg, getKillRegState(true))  in emitLoad()
1865     ResultReg = Reg64;  in emitLoad()
1867   return ResultReg;  in emitLoad()
1878   unsigned ResultReg;  in selectAddSub()  local
1883     ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));  in selectAddSub()
1886     ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));  in selectAddSub()
1889   if (!ResultReg)  in selectAddSub()
1892   updateValueMap(I, ResultReg);  in selectAddSub()
1904   unsigned ResultReg;  in selectLogicalOp()  local
1909     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
1912     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
1915     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
1918   if (!ResultReg)  in selectLogicalOp()
1921   updateValueMap(I, ResultReg);  in selectLogicalOp()
1973   unsigned ResultReg =  in selectLoad()  local
1975   if (!ResultReg)  in selectLoad()
2001           ResultReg = std::prev(I)->getOperand(0).getReg();  in selectLoad()
2004           ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,  in selectLoad()
2007       updateValueMap(I, ResultReg);  in selectLoad()
2028     updateValueMap(IntExtVal, ResultReg);  in selectLoad()
2032   updateValueMap(I, ResultReg);  in selectLoad()
2521   unsigned ResultReg = 0;  in selectCmp()  local
2526     ResultReg = createResultReg(&AArch64::GPR32RegClass);  in selectCmp()
2528             TII.get(TargetOpcode::COPY), ResultReg)  in selectCmp()
2532     ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);  in selectCmp()
2536   if (ResultReg) {  in selectCmp()
2537     updateValueMap(I, ResultReg);  in selectCmp()
2545   ResultReg = createResultReg(&AArch64::GPR32RegClass);  in selectCmp()
2573             ResultReg)  in selectCmp()
2578     updateValueMap(I, ResultReg);  in selectCmp()
2587           ResultReg)  in selectCmp()
2592   updateValueMap(I, ResultReg);  in selectCmp()
2644   Register ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,  in optimizeSelect()  local
2646   updateValueMap(SI, ResultReg);  in optimizeSelect()
2765   Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC);  in selectSelect()  local
2766   updateValueMap(I, ResultReg);  in selectSelect()
2779   Register ResultReg = createResultReg(&AArch64::FPR64RegClass);  in selectFPExt()  local
2781           ResultReg).addReg(Op);  in selectFPExt()
2782   updateValueMap(I, ResultReg);  in selectFPExt()
2795   Register ResultReg = createResultReg(&AArch64::FPR32RegClass);  in selectFPTrunc()  local
2797           ResultReg).addReg(Op);  in selectFPTrunc()
2798   updateValueMap(I, ResultReg);  in selectFPTrunc()
2828   Register ResultReg = createResultReg(  in selectFPToInt()  local
2830   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in selectFPToInt()
2832   updateValueMap(I, ResultReg);  in selectFPToInt()
2874   Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);  in selectIntToFP()  local
2875   updateValueMap(I, ResultReg);  in selectIntToFP()
2982     Register ResultReg = createResultReg(RC);  in fastLowerArguments()  local
2984             TII.get(TargetOpcode::COPY), ResultReg)  in fastLowerArguments()
2986     updateValueMap(&Arg, ResultReg);  in fastLowerArguments()
3107     Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));  in finishCall()  local
3109             TII.get(TargetOpcode::COPY), ResultReg)  in finishCall()
3113     CLI.ResultReg = ResultReg;  in finishCall()
3304     unsigned ResultReg = emitLoad(VT, VT, Src);  in tryEmitSmallMemCpy()  local
3305     if (!ResultReg)  in tryEmitSmallMemCpy()
3308     if (!emitStore(VT, ResultReg, Dest))  in tryEmitSmallMemCpy()
3448     Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);  in fastLowerIntrinsicCall()  local
3450             TII.get(AArch64::ADDXri), ResultReg)  in fastLowerIntrinsicCall()
3455     updateValueMap(II, ResultReg);  in fastLowerIntrinsicCall()
3559     updateValueMap(II, CLI.ResultReg);  in fastLowerIntrinsicCall()
3581     Register ResultReg = createResultReg(TLI.getRegClassFor(VT));  in fastLowerIntrinsicCall()  local
3582     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in fastLowerIntrinsicCall()
3584     updateValueMap(II, ResultReg);  in fastLowerIntrinsicCall()
3607     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg);  in fastLowerIntrinsicCall()  local
3608     if (!ResultReg)  in fastLowerIntrinsicCall()
3611     updateValueMap(II, ResultReg);  in fastLowerIntrinsicCall()
3898   unsigned ResultReg;  in selectTrunc()  local
3919     ResultReg = emitAnd_ri(MVT::i32, Reg32, Mask);  in selectTrunc()
3920     assert(ResultReg && "Unexpected AND instruction emission failure.");  in selectTrunc()
3922     ResultReg = createResultReg(&AArch64::GPR32RegClass);  in selectTrunc()
3924             TII.get(TargetOpcode::COPY), ResultReg)  in selectTrunc()
3928   updateValueMap(I, ResultReg);  in selectTrunc()
3941     unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1);  in emiti1Ext()  local
3942     assert(ResultReg && "Unexpected AND instruction emission failure.");  in emiti1Ext()
3950           .addReg(ResultReg)  in emiti1Ext()
3952       ResultReg = Reg64;  in emiti1Ext()
3954     return ResultReg;  in emiti1Ext()
4017   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);  in emitLSL_rr()  local
4019     ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);  in emitLSL_rr()
4020   return ResultReg;  in emitLSL_rr()
4043       Register ResultReg = createResultReg(RC);  in emitLSL_ri()  local
4045               TII.get(TargetOpcode::COPY), ResultReg)  in emitLSL_ri()
4047       return ResultReg;  in emitLSL_ri()
4120   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);  in emitLSR_rr()  local
4122     ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);  in emitLSR_rr()
4123   return ResultReg;  in emitLSR_rr()
4146       Register ResultReg = createResultReg(RC);  in emitLSR_ri()  local
4148               TII.get(TargetOpcode::COPY), ResultReg)  in emitLSR_ri()
4150       return ResultReg;  in emitLSR_ri()
4236   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);  in emitASR_rr()  local
4238     ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);  in emitASR_rr()
4239   return ResultReg;  in emitASR_rr()
4262       Register ResultReg = createResultReg(RC);  in emitASR_ri()  local
4264               TII.get(TargetOpcode::COPY), ResultReg)  in emitASR_ri()
4266       return ResultReg;  in emitASR_ri()
4509         Register ResultReg = createResultReg(&AArch64::GPR64RegClass);  in selectIntExt()  local
4511                 TII.get(AArch64::SUBREG_TO_REG), ResultReg)  in selectIntExt()
4515         SrcReg = ResultReg;  in selectIntExt()
4523   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);  in selectIntExt()  local
4524   if (!ResultReg)  in selectIntExt()
4527   updateValueMap(I, ResultReg);  in selectIntExt()
4567   Register ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg);  in selectRem()  local
4568   updateValueMap(I, ResultReg);  in selectRem()
4616       unsigned ResultReg =  in selectMul()  local
4619       if (ResultReg) {  in selectMul()
4620         updateValueMap(I, ResultReg);  in selectMul()
4633   unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg);  in selectMul()  local
4635   if (!ResultReg)  in selectMul()
4638   updateValueMap(I, ResultReg);  in selectMul()
4651     unsigned ResultReg = 0;  in selectShift()  local
4683       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4686       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4689       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4692     if (!ResultReg)  in selectShift()
4695     updateValueMap(I, ResultReg);  in selectShift()
4707   unsigned ResultReg = 0;  in selectShift()  local
4711     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op1Reg);  in selectShift()
4714     ResultReg = emitASR_rr(RetVT, Op0Reg, Op1Reg);  in selectShift()
4717     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op1Reg);  in selectShift()
4721   if (!ResultReg)  in selectShift()
4724   updateValueMap(I, ResultReg);  in selectShift()
4760   Register ResultReg = fastEmitInst_r(Opc, RC, Op0Reg);  in selectBitCast()  local
4761   if (!ResultReg)  in selectBitCast()
4764   updateValueMap(I, ResultReg);  in selectBitCast()
4802   updateValueMap(I, CLI.ResultReg);  in selectFRem()
4825     unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2);  in selectSDiv()  local
4826     if (!ResultReg)  in selectSDiv()
4828     updateValueMap(I, ResultReg);  in selectSDiv()
4858   unsigned ResultReg;  in selectSDiv()  local
4860     ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg,  in selectSDiv()
4863     ResultReg = emitASR_ri(VT, VT, SelectReg, Lg2);  in selectSDiv()
4865   if (!ResultReg)  in selectSDiv()
4868   updateValueMap(I, ResultReg);  in selectSDiv()