Lines Matching refs:ResultReg
79 unsigned &ResultReg, unsigned Alignment = 1);
87 unsigned &ResultReg);
319 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
468 ResultReg = createResultReg(RC); in X86FastEmitLoad()
470 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in X86FastEmitLoad()
703 unsigned &ResultReg) { in X86FastEmitExtend() argument
708 ResultReg = RR; in X86FastEmitExtend()
1344 unsigned ResultReg = 0; in X86SelectLoad() local
1345 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1349 updateValueMap(I, ResultReg); in X86SelectLoad()
1453 unsigned ResultReg = 0; in X86SelectCmp() local
1457 ResultReg = createResultReg(&X86::GR32RegClass); in X86SelectCmp()
1459 ResultReg); in X86SelectCmp()
1460 ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg, X86::sub_8bit); in X86SelectCmp()
1461 if (!ResultReg) in X86SelectCmp()
1466 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1468 ResultReg).addImm(1); in X86SelectCmp()
1473 if (ResultReg) { in X86SelectCmp()
1474 updateValueMap(I, ResultReg); in X86SelectCmp()
1502 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1514 ResultReg).addReg(FlagReg1).addReg(FlagReg2); in X86SelectCmp()
1515 updateValueMap(I, ResultReg); in X86SelectCmp()
1532 ResultReg).addImm(CC); in X86SelectCmp()
1533 updateValueMap(I, ResultReg); in X86SelectCmp()
1542 Register ResultReg = getRegForValue(I->getOperand(0)); in X86SelectZExt() local
1543 if (ResultReg == 0) in X86SelectZExt()
1550 ResultReg = fastEmitZExtFromI1(MVT::i8, ResultReg); in X86SelectZExt()
1553 if (ResultReg == 0) in X86SelectZExt()
1570 .addReg(ResultReg); in X86SelectZExt()
1572 ResultReg = createResultReg(&X86::GR64RegClass); in X86SelectZExt()
1574 ResultReg) in X86SelectZExt()
1581 Result32).addReg(ResultReg); in X86SelectZExt()
1583 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, X86::sub_16bit); in X86SelectZExt()
1585 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
1586 ResultReg); in X86SelectZExt()
1587 if (ResultReg == 0) in X86SelectZExt()
1591 updateValueMap(I, ResultReg); in X86SelectZExt()
1600 Register ResultReg = getRegForValue(I->getOperand(0)); in X86SelectSExt() local
1601 if (ResultReg == 0) in X86SelectSExt()
1608 Register ZExtReg = fastEmitZExtFromI1(MVT::i8, ResultReg); in X86SelectSExt()
1613 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectSExt()
1615 ResultReg).addReg(ZExtReg); in X86SelectSExt()
1625 Result32).addReg(ResultReg); in X86SelectSExt()
1627 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, X86::sub_16bit); in X86SelectSExt()
1629 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND, in X86SelectSExt()
1630 ResultReg); in X86SelectSExt()
1631 if (ResultReg == 0) in X86SelectSExt()
1635 updateValueMap(I, ResultReg); in X86SelectSExt()
1855 Register ResultReg = createResultReg(RC); in X86SelectShift() local
1856 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg) in X86SelectShift()
1858 updateValueMap(I, ResultReg); in X86SelectShift()
1998 unsigned ResultReg = 0; in X86SelectDivRem() local
2012 ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultSuperReg, in X86SelectDivRem()
2016 if (!ResultReg) { in X86SelectDivRem()
2017 ResultReg = createResultReg(TypeEntry.RC); in X86SelectDivRem()
2018 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg) in X86SelectDivRem()
2021 updateValueMap(I, ResultReg); in X86SelectDivRem()
2143 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); in X86FastEmitCMoveSelect() local
2144 updateValueMap(I, ResultReg); in X86FastEmitCMoveSelect()
2199 unsigned ResultReg; in X86FastEmitSSESelect() local
2224 ResultReg = createResultReg(RC); in X86FastEmitSSESelect()
2226 TII.get(TargetOpcode::COPY), ResultReg).addReg(MovReg); in X86FastEmitSSESelect()
2245 ResultReg = createResultReg(RC); in X86FastEmitSSESelect()
2247 TII.get(TargetOpcode::COPY), ResultReg).addReg(VBlendReg); in X86FastEmitSSESelect()
2267 ResultReg = createResultReg(RC); in X86FastEmitSSESelect()
2269 TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg); in X86FastEmitSSESelect()
2271 updateValueMap(I, ResultReg); in X86FastEmitSSESelect()
2343 Register ResultReg = in X86FastEmitPseudoSelect() local
2345 updateValueMap(I, ResultReg); in X86FastEmitPseudoSelect()
2369 Register ResultReg = createResultReg(RC); in X86SelectSelect() local
2371 TII.get(TargetOpcode::COPY), ResultReg) in X86SelectSelect()
2373 updateValueMap(I, ResultReg); in X86SelectSelect()
2442 Register ResultReg = fastEmitInst_rr(Opcode, RC, ImplicitDefReg, OpReg); in X86SelectIntToFP() local
2443 updateValueMap(I, ResultReg); in X86SelectIntToFP()
2476 Register ResultReg = createResultReg(RC); in X86SelectFPExtOrFPTrunc() local
2479 ResultReg); in X86SelectFPExtOrFPTrunc()
2485 updateValueMap(I, ResultReg); in X86SelectFPExtOrFPTrunc()
2539 Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, InputReg, in X86SelectTrunc() local
2541 if (!ResultReg) in X86SelectTrunc()
2544 updateValueMap(I, ResultReg); in X86SelectTrunc()
2612 unsigned ResultReg = 0; in fastLowerIntrinsicCall() local
2629 ResultReg = createResultReg(&X86::GR32RegClass); in fastLowerIntrinsicCall()
2630 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
2635 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, RegIdx); in fastLowerIntrinsicCall()
2651 ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in fastLowerIntrinsicCall()
2653 TII.get(TargetOpcode::COPY), ResultReg) in fastLowerIntrinsicCall()
2657 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
2834 Register ResultReg = createResultReg(RC); in fastLowerIntrinsicCall() local
2837 ResultReg); in fastLowerIntrinsicCall()
2844 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
2897 unsigned ResultReg = 0; in fastLowerIntrinsicCall() local
2908 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
2911 TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg) in fastLowerIntrinsicCall()
2914 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, CI->getZExtValue()); in fastLowerIntrinsicCall()
2918 if (!ResultReg) { in fastLowerIntrinsicCall()
2922 ResultReg = fastEmit_rr(VT, VT, BaseOpc, LHSReg, RHSReg); in fastLowerIntrinsicCall()
2927 if (BaseOpc == X86ISD::UMUL && !ResultReg) { in fastLowerIntrinsicCall()
2936 ResultReg = fastEmitInst_r(MULOpc[VT.SimpleTy-MVT::i8], in fastLowerIntrinsicCall()
2938 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { in fastLowerIntrinsicCall()
2947 ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg); in fastLowerIntrinsicCall()
2949 ResultReg = fastEmitInst_rr(MULOpc[VT.SimpleTy-MVT::i8], in fastLowerIntrinsicCall()
2953 if (!ResultReg) in fastLowerIntrinsicCall()
2958 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers."); in fastLowerIntrinsicCall()
2962 updateValueMap(II, ResultReg, 2); in fastLowerIntrinsicCall()
3028 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall() local
3029 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3032 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3127 Register ResultReg = createResultReg(RC); in fastLowerArguments() local
3129 TII.get(TargetOpcode::COPY), ResultReg) in fastLowerArguments()
3131 updateValueMap(&Arg, ResultReg); in fastLowerArguments()
3252 unsigned ResultReg; in fastLowerCall() local
3256 ResultReg = getRegForValue(PrevVal); in fastLowerCall()
3258 if (!ResultReg) in fastLowerCall()
3264 ResultReg = fastEmit_ri(VT, VT, ISD::AND, ResultReg, 1); in fastLowerCall()
3269 ResultReg = getRegForValue(Val); in fastLowerCall()
3272 if (!ResultReg) in fastLowerCall()
3275 ArgRegs.push_back(ResultReg); in fastLowerCall()
3531 Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy); in fastLowerCall() local
3535 unsigned CopyReg = ResultReg + i; in fastLowerCall()
3570 TII.get(Opc), ResultReg + i), FI); in fastLowerCall()
3574 CLI.ResultReg = ResultReg; in fastLowerCall()
3657 Register ResultReg = createResultReg(DstClass); in fastSelectInstruction() local
3659 TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg); in fastSelectInstruction()
3661 updateValueMap(I, ResultReg); in fastSelectInstruction()
3686 Register ResultReg = createResultReg(&X86::GR64RegClass); in X86MaterializeInt() local
3688 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) in X86MaterializeInt()
3690 return ResultReg; in X86MaterializeInt()
3766 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in X86MaterializeFP() local
3775 TII.get(Opc), ResultReg); in X86MaterializeFP()
3781 return ResultReg; in X86MaterializeFP()
3785 TII.get(Opc), ResultReg), in X86MaterializeFP()
3787 return ResultReg; in X86MaterializeFP()
3804 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in X86MaterializeGV() local
3810 ResultReg) in X86MaterializeGV()
3818 TII.get(Opc), ResultReg), AM); in X86MaterializeGV()
3820 return ResultReg; in X86MaterializeGV()
3858 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastMaterializeConstant() local
3860 ResultReg); in fastMaterializeConstant()
3861 return ResultReg; in fastMaterializeConstant()
3888 Register ResultReg = createResultReg(RC); in fastMaterializeAlloca() local
3890 TII.get(Opc), ResultReg), AM); in fastMaterializeAlloca()
3891 return ResultReg; in fastMaterializeAlloca()
3924 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastMaterializeFloatZero() local
3925 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in fastMaterializeFloatZero()
3926 return ResultReg; in fastMaterializeFloatZero()
3982 Register ResultReg = createResultReg(RC); in fastEmitInst_rrrr() local
3989 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rrrr()
4001 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrrr()
4003 return ResultReg; in fastEmitInst_rrrr()