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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp148 for (auto Reg : Regs) in getFrameHelperName()
276 assert(Regs.size() >= 2); in getOrCreateFrameHelper()
293 Regs.begin(), std::find(Regs.begin(), Regs.end(), AArch64::LR)); in getOrCreateFrameHelper()
299 emitStore(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], in getOrCreateFrameHelper()
308 emitStore(MF, MBB, MBB.end(), TII, Regs[I - 1], Regs[I], Size - I - 1, in getOrCreateFrameHelper()
334 emitLoad(MF, MBB, MBB.end(), TII, Regs[I], Regs[I + 1], Size - I - 2, in getOrCreateFrameHelper()
337 emitLoad(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], Size, in getOrCreateFrameHelper()
471 emitLoad(MF, MBB, MBBI, *TII, Regs[I], Regs[I + 1], Size - I - 2, false); in lowerEpilog()
473 emitLoad(MF, MBB, MBBI, *TII, Regs[Size - 2], Regs[Size - 1], Size, true); in lowerEpilog()
552 emitStore(MF, MBB, MBBI, *TII, Regs[Size - 2], Regs[Size - 1], -Size, true); in lowerProlog()
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/llvm-project-15.0.7/llvm/test/TableGen/
H A DAsmPredicateCombiningRISCV.td23 def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>;
28 let InOperandList = (ins Regs:$r);
38 let InOperandList = (ins Regs:$r);
61 def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
67 def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
74 def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
80 def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;
88 def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
H A DInsufficientPositionalOperands.td16 def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>;
28 let OutOperandList = (outs Regs:$xd);
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h335 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
336 if (!isAllocated(Regs[i])) in getFirstUnallocated()
338 return Regs.size(); in getFirstUnallocated()
368 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
370 if (FirstUnalloc == Regs.size()) in AllocateReg()
374 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
383 if (RegsRequired > Regs.size()) in AllocateRegBlock()
391 if (isAllocated(Regs[StartIdx + BlockIdx])) { in AllocateRegBlock()
399 MarkAllocated(Regs[StartIdx + BlockIdx]); in AllocateRegBlock()
401 return Regs[StartIdx]; in AllocateRegBlock()
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H A DRegisterPressure.h274 RegSet Regs; variable
296 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
297 if (I == Regs.end()) in contains()
306 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
319 RegSet::iterator I = Regs.find(SparseIndex); in erase()
320 if (I == Regs.end()) in erase()
328 return Regs.size(); in size()
333 for (const IndexMaskPair &P : Regs) { in appendTo()
410 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp84 RegNo = Regs[RegNo]; in decodeRegisterClass()
302 const unsigned *Regs) { in decodeBDAddr12Operand() argument
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
312 const unsigned *Regs) { in decodeBDAddr20Operand() argument
316 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
322 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
327 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
334 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
370 const unsigned *Regs) { in decodeBDRAddr12Operand() argument
377 Inst.addOperand(MCOperand::createReg(Regs[Length])); in decodeBDRAddr12Operand()
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/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp329 BitVector &Regs) const { in getClobberedRegs()
337 Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false); in getClobberedRegs()
354 Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false); in getTouchedRegs()
357 Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false); in getTouchedRegs()
374 Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true); in getWrittenRegs()
391 Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true); in getUsedRegs()
405 BitVector CallRegs = BitVector(Regs.size(), false); in getSrcRegs()
408 Regs |= CallRegs; in getSrcRegs()
413 getDefaultLiveOut(Regs); in getSrcRegs()
418 getRepRegs(Regs); in getSrcRegs()
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/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp35 SmallVector<Register, 1> Regs; member in __anon17f87c980111::GISelAsmOperandInfo
132 OpInfo.Regs.push_back(R); in getRegistersForValue()
398 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
409 OpInfo.Regs.size()); in lowerInlineAsm()
421 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
545 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
573 Inst.addReg(OpInfo.Regs[0]); in lowerInlineAsm()
585 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
611 if (OpInfo.Regs.empty()) in lowerInlineAsm()
617 if (OpInfo.Regs.size() > 1) { in lowerInlineAsm()
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H A DCallLowering.cpp329 assert(OrigRegs[0] == Regs[0]); in buildCopyFromRegs()
334 Regs.size() == 1) { in buildCopyFromRegs()
346 Register SrcReg = Regs[0]; in buildCopyFromRegs()
376 B.buildMerge(OrigRegs[0], Regs); in buildCopyFromRegs()
387 SmallVector<Register> CastRegs(Regs.begin(), Regs.end()); in buildCopyFromRegs()
394 Regs.size() == 1) { in buildCopyFromRegs()
432 for (Register Reg : Regs) in buildCopyFromRegs()
450 Regs = Regs.drop_front(PartsPerElt); in buildCopyFromRegs()
683 Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end()); in handleAssignments()
688 Args[i].Regs.resize(NumParts); in handleAssignments()
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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp389 for (auto &RE : Regs) { in EmitRegMappingTables()
450 for (auto &RE : Regs) { in EmitRegMappingTables()
514 for (auto &RE : Regs) { in EmitRegMapping()
908 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { in runMCDesc()
943 if (I != Regs.begin() && in runMCDesc()
1014 for (const auto &Reg : Regs) { in runMCDesc()
1108 for (const auto &RE : Regs) { in runMCDesc()
1135 EmitRegMapping(OS, Regs, false); in runMCDesc()
1458 for (const auto &Reg : Regs) in runTargetDesc()
1468 for (const auto &Reg : Regs) { in runTargetDesc()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h63 SmallVector<Register, 4> Regs; member
81 ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
84 : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()), in BaseArgInfo()
86 if (!Regs.empty() && Flags.empty()) in BaseArgInfo()
90 (Regs.empty() || Regs[0] == 0)) && in BaseArgInfo()
94 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue, unsigned OrigIndex,
97 : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed, &OrigValue) {}
282 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA); in assignValueToAddress()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp773 return Regs; in getRegsUsedAsParams()
788 Regs.set(X86::RAX); in getDefaultDefIn()
789 Regs.set(X86::RCX); in getDefaultDefIn()
790 Regs.set(X86::RDX); in getDefaultDefIn()
791 Regs.set(X86::RSI); in getDefaultDefIn()
792 Regs.set(X86::RDI); in getDefaultDefIn()
793 Regs.set(X86::R8); in getDefaultDefIn()
794 Regs.set(X86::R9); in getDefaultDefIn()
834 Regs.set(X86::RAX); in getGPRegs()
841 Regs.set(X86::R8); in getGPRegs()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.cpp110 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
111 while (Regs) { in EmitVFPRegSave()
113 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
114 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
124 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DReachingDefOrUse.h133 BitVector Regs = BitVector(this->BC.MRI->getNumRegs(), false); in computeNext() local
135 RA.getInstClobberList(Point, Regs); in computeNext()
137 RA.getInstUsedRegsList(Point, Regs, false); in computeNext()
138 Regs &= this->BC.MIB->getAliases(*TrackingReg); in computeNext()
139 if (Regs.any()) in computeNext()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp919 auto *Regs = in isXPLeafCandidate() local
1065 SavedRegs.set(Regs.getFramePointerRegister()); in determineCalleeSaves()
1095 MIB.addReg(Regs.getStackPointerRegister()); in spillCalleeSavedRegisters()
1163 .addReg(Regs.getStackPointerRegister()) in restoreCalleeSavedRegisters()
1175 MIB.addReg(Regs.getStackPointerRegister()); in restoreCalleeSavedRegisters()
1270 Regs.getFramePointerRegister()) in emitPrologue()
1271 .addReg(Regs.getStackPointerRegister()); in emitPrologue()
1277 B.addLiveIn(Regs.getFramePointerRegister()); in emitPrologue()
1295 unsigned SPReg = Regs.getStackPointerRegister(); in emitEpilogue()
1390 auto *Regs = in determineFrameLayout() local
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H A DSystemZRegisterInfo.cpp244 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
246 return Regs->getCalleeSavedRegs(MF); in getCalleeSavedRegs()
254 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
255 return Regs->getCallPreservedMask(MF, CC); in getCallPreservedMask()
263 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
266 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true); in getReservedRegs()
271 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true); in getReservedRegs()
454 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getFrameRegister() local
456 return TFI->hasFP(MF) ? Regs->getFramePointerRegister() in getFrameRegister()
457 : Regs->getStackPointerRegister(); in getFrameRegister()
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DHWEventListener.h75 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
78 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
96 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
98 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/
H A DTaint.cpp138 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
140 Regs = F.add(Regs, SubRegion, Kind); in addPartialTaint()
141 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs); in addPartialTaint()
204 if (const TaintedSubRegions *Regs = in isTainted() local
207 for (auto I : *Regs) { in isTainted()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp877 const unsigned *Regs; in parseRegister() local
892 if (Regs[Reg.Num] == 0) { in parseRegister()
1124 const unsigned *Regs; in parseAddress() local
1126 case GR32Reg: Regs = SystemZMC::GR32Regs; break; in parseAddress()
1137 Base = Regs[Reg1.Num]; in parseAddress()
1153 Index = Regs[Reg1.Num]; in parseAddress()
1155 Base = Regs[Reg1.Num]; in parseAddress()
1161 Base = Regs[Reg2.Num]; in parseAddress()
1169 Base = Regs[Reg2.Num]; in parseAddress()
1193 Base = Regs[Reg2.Num]; in parseAddress()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp162 auto Regs = getRegisters(); in getRegister() local
163 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
164 if (It == Regs.end()) in getRegister()
674 auto Regs = getRegisters(); in toString() local
675 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { in toString()
676 if (I != Regs.begin()) in toString()
/llvm-project-15.0.7/llvm/test/tools/llvm-pdbutil/
H A Dfpo-data.test6 CHECK-NEXT: RVA | Code | Locals | Params | Prolog | Saved Regs | Use BP | Has SEH | Frame Type
11 CHECK-NEXT: RVA | Code | Locals | Params | Stack | Prolog | Saved Regs | Has SEH | Has C++EH |…
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp329 SmallVector<int, 4> Regs; in visitSoftInstr() local
341 auto I = partition_point(Regs, [&](int I) { in visitSoftInstr()
344 Regs.insert(I, rx); in visitSoftInstr()
350 while (!Regs.empty()) { in visitSoftInstr()
352 dv = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVCallLowering.cpp265 if (Info.OrigRet.Regs.size() > 1) in lowerCall()
284 Info.OrigRet.Regs.empty() ? Register(0) : Info.OrigRet.Regs[0]; in lowerCall()
321 if (Arg.Regs.size() > 1) in lowerCall()
323 MIB.addUse(Arg.Regs[0]); in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp309 Register ValVReg = Arg.Regs[RegIndex]; in assignValueToAddress()
446 if (CurVReg != CurArgInfo.Regs[0]) { in lowerReturn()
447 CurArgInfo.Regs[0] = CurVReg; in lowerReturn()
568 assert(OrigArg.Regs.size() == 1 && in lowerFormalArguments()
569 MRI.getType(OrigArg.Regs[0]).getSizeInBits() == 1 && in lowerFormalArguments()
574 Register OrigReg = OrigArg.Regs[0]; in lowerFormalArguments()
576 OrigArg.Regs[0] = WideReg; in lowerFormalArguments()
1107 assert(OutArg.Regs.size() == 1 && in lowerCall()
1108 MRI.getType(OutArg.Regs[0]).getSizeInBits() == 1 && in lowerCall()
1113 OutArg.Regs[0] = in lowerCall()
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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString() argument
84 for (const unsigned Reg : Regs.set_bits()) { in debugString()

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