1// RUN: not llvm-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s
2
3// Check that TableGen doesn't crash on insufficient positional
4// instruction operands.
5
6include "llvm/Target/Target.td"
7
8def ArchInstrInfo : InstrInfo { }
9
10def Arch : Target {
11  let InstructionSet = ArchInstrInfo;
12}
13
14def Reg : Register<"reg">;
15
16def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>;
17
18def foo : Instruction {
19  bits<3> rd;
20  bits<3> rs;
21
22  bits<8> Inst;
23  let Inst{1-0} = 0;
24  let Inst{4-2} = rd;
25  let Inst{7-5} = rs;
26
27// CHECK: Too few operands in record foo (no match for variable rs)
28  let OutOperandList = (outs Regs:$xd);
29  let InOperandList = (ins);
30}
31