86   void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
89                             const std::deque<CodeGenRegister> &Regs,
218     const CodeGenRegister::Vec &Regs = RC.getMembers();  in EmitRegUnitPressure()  local
220     if (Regs.empty() || RC.Artificial)  in EmitRegUnitPressure()
383     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {  in EmitRegMappingTables()  argument
389   for (auto &RE : Regs) {  in EmitRegMappingTables()
405   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");  in EmitRegMappingTables()
450   for (auto &RE : Regs) {  in EmitRegMappingTables()
510     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {  in EmitRegMapping()  argument
514   for (auto &RE : Regs) {  in EmitRegMapping()
523   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");  in EmitRegMapping()
880   const auto &Regs = RegBank.getRegisters();  in runMCDesc()  local
889   SmallVector<DiffVec, 4> SubRegLists(Regs.size());  in runMCDesc()
890   SmallVector<DiffVec, 4> SuperRegLists(Regs.size());  in runMCDesc()
891   SmallVector<DiffVec, 4> RegUnitLists(Regs.size());  in runMCDesc()
892   SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());  in runMCDesc()
896   SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());  in runMCDesc()
902   SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());  in runMCDesc()
908   for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {  in runMCDesc()
943     if (I != Regs.begin() &&  in runMCDesc()
946     if (std::next(I) != Regs.end() &&  in runMCDesc()
1014   for (const auto &Reg : Regs) {  in runMCDesc()
1101   EmitRegMappingTables(OS, Regs, false);  in runMCDesc()
1108   for (const auto &RE : Regs) {  in runMCDesc()
1126      << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "  in runMCDesc()
1135   EmitRegMapping(OS, Regs, false);  in runMCDesc()
1456   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()  local
1458   for (const auto &Reg : Regs)  in runTargetDesc()
1462   llvm::BitVector InAllocClass(Regs.size() + 1, false);  in runTargetDesc()
1468   for (const auto &Reg : Regs) {  in runTargetDesc()
1559   EmitRegMappingTables(OS, Regs, true);  in runTargetDesc()
1571      << "  InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1  in runTargetDesc()
1585   EmitRegMapping(OS, Regs, true);  in runTargetDesc()
1594     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()  local
1595     assert(Regs && "Cannot expand CalleeSavedRegs instance");  in runTargetDesc()
1600     for (unsigned r = 0, re = Regs->size(); r != re; ++r)  in runTargetDesc()
1601       OS << getQualifiedName((*Regs)[r]) << ", ";  in runTargetDesc()
1605     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()