152         Info.OrigRet.Regs[0] = ReturnHintAlignReg;  in lowerCall()
251     SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),  in splitToValueTypes()
258   assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");  in splitToValueTypes()
264     SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex,  in splitToValueTypes()
322                               ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,  in buildCopyFromRegs()  argument
329     assert(OrigRegs[0] == Regs[0]);  in buildCopyFromRegs()
334       Regs.size() == 1) {  in buildCopyFromRegs()
335     B.buildBitcast(OrigRegs[0], Regs[0]);  in buildCopyFromRegs()
345       OrigRegs.size() == 1 && Regs.size() == 1) {  in buildCopyFromRegs()
346     Register SrcReg = Regs[0];  in buildCopyFromRegs()
374     unsigned SrcSize = PartLLT.getSizeInBits().getFixedSize() * Regs.size();  in buildCopyFromRegs()
376       B.buildMerge(OrigRegs[0], Regs);  in buildCopyFromRegs()
378       auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);  in buildCopyFromRegs()
387     SmallVector<Register> CastRegs(Regs.begin(), Regs.end());  in buildCopyFromRegs()
394         Regs.size() == 1) {  in buildCopyFromRegs()
397       CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);  in buildCopyFromRegs()
432       for (Register Reg : Regs)  in buildCopyFromRegs()
436     B.buildBuildVector(OrigRegs[0], Regs);  in buildCopyFromRegs()
446       auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt));  in buildCopyFromRegs()
450       Regs = Regs.drop_front(PartsPerElt);  in buildCopyFromRegs()
458     auto BV = B.buildBuildVector(BVType, Regs);  in buildCopyFromRegs()
683     Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());  in handleAssignments()
688       Args[i].Regs.resize(NumParts);  in handleAssignments()
694         Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);  in handleAssignments()
703       buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,  in handleAssignments()
709       Register ArgReg = Args[i].Regs[Part];  in handleAssignments()
732         assert(Args[i].Regs.size() == 1 &&  in handleAssignments()
740           MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);  in handleAssignments()
766           Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],  in handleAssignments()
796       buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,  in handleAssignments()
981     if (OutInfo.Regs.size() > 1) {  in parametersInCSRMatch()
990     MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);  in parametersInCSRMatch()