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Searched refs:RegTy (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td132 class PatFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
133 : Pat<(OpNode RegTy:$fj), (Inst $fj)>;
134 class PatFprFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
135 : Pat<(OpNode RegTy:$fj, RegTy:$fk), (Inst $fj, $fk)>;
154 class PatFPSetcc<CondCode cc, LAInst CmpInst, RegisterClass RegTy>
155 : Pat<(setcc RegTy:$fj, RegTy:$fk, cc),
156 (MOVCF2GR (CmpInst RegTy:$fj, RegTy:$fk))>;
180 RegisterClass RegTy>
181 : Pat<(select (GRLenVT (setcc RegTy:$a, RegTy:$b, cc)), RegTy:$t, RegTy:$f),
182 (SelInst RegTy:$f, RegTy:$t, (CmpInst RegTy:$a, RegTy:$b))>;
/llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/
H A DReduceInstructionsMIR.cpp101 LLT RegTy = MRI->getType(Reg); in extractInstrFromFunction() local
112 NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, RegTy, ToDelete); in extractInstrFromFunction()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp451 LLT RegTy = MRI.getType(Op.getReg()); in getInstrMapping() local
453 if (RegTy.isScalar() && in getInstrMapping()
454 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64)) in getInstrMapping()
457 if (RegTy.isVector() && RegTy.getSizeInBits() != 128) in getInstrMapping()
H A DMipsCallLowering.cpp428 LLT RegTy = LLT::scalar(RegSize * 8); in lowerFormalArguments() local
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
437 MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize)); in lowerFormalArguments()
H A DMipsISelLowering.cpp4383 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); in copyByValRegs() local
4384 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
4392 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
4412 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in passByValArg() local
4424 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, in passByValArg()
4451 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
4463 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, in passByValArg()
4467 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); in passByValArg()
4502 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in writeVarArgRegs() local
4503 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp173 LLT RegTy = MRI->getType(MO.getReg()); in repairReg() local
176 if (RegTy.isVector()) { in repairReg()
177 if (ValMapping.NumBreakDowns == RegTy.getNumElements()) in repairReg()
182 RegTy.getSizeInBits()) && in repairReg()
183 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() == in repairReg()
H A DUtils.cpp716 const DebugLoc &DL, LLT RegTy) { in getFunctionLiveInPhysReg() argument
734 if (RegTy.isValid()) in getFunctionLiveInPhysReg()
735 MRI.setType(LiveIn, RegTy); in getFunctionLiveInPhysReg()
H A DCallLowering.cpp1207 const LLT RegTy = MRI.getType(ValVReg); in assignValueToReg() local
1209 if (isCopyCompatibleType(RegTy, LocTy)) { in assignValueToReg()
1215 auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy); in assignValueToReg()
H A DLegalizerHelper.cpp163 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, in extractParts() argument
169 unsigned RegSize = RegTy.getSizeInBits(); in extractParts()
213 LLT RegTy = MRI.getType(Reg); in extractVectorParts() local
214 assert(RegTy.isVector() && "Expected a vector type"); in extractVectorParts()
216 LLT EltTy = RegTy.getElementType(); in extractVectorParts()
218 unsigned RegNumElts = RegTy.getNumElements(); in extractVectorParts()
5082 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); in narrowScalarAddSub() local
5086 extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left); in narrowScalarAddSub()
5117 insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy, in narrowScalarAddSub()
5258 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); in narrowScalarInsert() local
[all …]
H A DCombinerHelper.cpp707 LLT RegTy = MRI.getType(LoadReg); in matchCombineLoadWithAndMask() local
709 unsigned RegSize = RegTy.getSizeInBits(); in matchCombineLoadWithAndMask()
740 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
820 LLT RegTy = MRI.getType(DstReg); in matchSextInRegOfLoad() local
823 if (RegTy.isVector()) in matchSextInRegOfLoad()
853 else if (MemBits > NewSizeBits || MemBits == RegTy.getSizeInBits()) in matchSextInRegOfLoad()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp1489 const LLT RegTy = MRI.getType(DstReg); in selectDivRem() local
1490 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectDivRem()
1564 auto OpEntryIt = llvm::find_if(OpTable, [RegTy](const DivRemEntry &El) { in selectDivRem()
1565 return El.SizeInBits == RegTy.getSizeInBits(); in selectDivRem()
1591 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); in selectDivRem()
1617 if (RegTy.getSizeInBits() == 16) { in selectDivRem()
1621 } else if (RegTy.getSizeInBits() == 32) { in selectDivRem()
1625 } else if (RegTy.getSizeInBits() == 64) { in selectDivRem()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp93 const LLT RegTy = getType(Reg); in constrainRegAttrs() local
95 if (RegTy.isValid() && ConstrainingRegTy.isValid() && in constrainRegAttrs()
96 RegTy != ConstrainingRegTy) in constrainRegAttrs()
/llvm-project-15.0.7/llvm/tools/llvm-reduce/
H A DReducerWorkItem.cpp258 LLT RegTy = SrcMRI->getType(Reg); in cloneMF() local
259 if (RegTy.isValid()) in cloneMF()
260 DstMRI->setType(NewReg, RegTy); in cloneMF()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoF.td478 RegisterClass RegTy>
479 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>;
482 RegisterClass RegTy>
483 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>;
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h316 const DebugLoc &DL, LLT RegTy = LLT());
H A DLegalizerHelper.h193 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td4807 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4809 [(set (AccumTy RegTy:$dst),
4875 (ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
4890 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4902 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
9156 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
9157 [(set (AccumTy RegTy:$dst),
9170 (ins RegTy:$Vd, RegTy:$Vn,
9185 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
9194 class BF16MM<bit Q, RegisterClass RegTy,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp200 struct RegTy { struct
210 struct RegTy Reg;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp5062 LLT RegTy; in legalizeImageIntrinsic() local
5068 RegTy = S32; in legalizeImageIntrinsic()
5076 RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32; in legalizeImageIntrinsic()
5130 ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy); in legalizeImageIntrinsic()
5160 if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) { in legalizeImageIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1638 template <VecListIndexType RegTy, unsigned NumRegs>
1653 assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) && in addVectorListOperands()
1656 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands()
1658 FirstRegs[(unsigned)RegTy][0])); in addVectorListOperands()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp3201 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32; in SelectCMP_SWAP() local
3206 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops); in SelectCMP_SWAP()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DTargetInfo.cpp5374 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits); in classifyArgumentType() local
5375 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs); in classifyArgumentType()