llvm-reduce: Add reduction for custom register masks

I have a register allocator failure that only reproduces with IPRA
enabled, and requires the specific regmask if I want to only run the
one relev

llvm-reduce: Add reduction for custom register masks

I have a register allocator failure that only reproduces with IPRA
enabled, and requires the specific regmask if I want to only run the
one relevant pass. The printed custom regmask is enormous and I would
like to reduce it.

This reduces each individual bit in the mask, but it would probably be
better to start at register units and clear all aliasing fields at a
time. This would require stricter verification that all aliasing bits
are set in regmasks (although I would prefer to switch regmasks to use
register units in the first place).

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[llvm-reduce] Add support for LTO bitcode files

Adds support for reading and writing LTO bitcode files.

- Emit a summary if the original bitcode file had a summary
- Use split LTO units if the

[llvm-reduce] Add support for LTO bitcode files

Adds support for reading and writing LTO bitcode files.

- Emit a summary if the original bitcode file had a summary
- Use split LTO units if the original bitcode file used them.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D127168

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llvm-reduce: Add cloning of target MachineFunctionInfo

MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to Ma

llvm-reduce: Add cloning of target MachineFunctionInfo

MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to MachineFunctionInfo. This is a subtle variant of
the copy constructor that is required if there are any MIR constructs
that use pointers. Specifically, at minimum fields that reference
MachineBasicBlocks or the MachineFunction need to be adjusted to the
values in the new function.

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llvm-reduce: Don't assert on functions which don't track liveness

Use the query that doesn't assert if TracksLiveness isn't set, which
needs to always be available. We also need to start printing li

llvm-reduce: Don't assert on functions which don't track liveness

Use the query that doesn't assert if TracksLiveness isn't set, which
needs to always be available. We also need to start printing liveins
regardless of TracksLiveness.

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[tools] Forward declare classes & remove includes

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D120208

llvm-reduce: Add reduction pass to remove regalloc hints

I'm a bit confused by what's actually stored for the allocation
hints. The MIR parser only handles the "simple" case where there's a
single h

llvm-reduce: Add reduction pass to remove regalloc hints

I'm a bit confused by what's actually stored for the allocation
hints. The MIR parser only handles the "simple" case where there's a
single hint. I don't really understand the assertion in
clearSimpleHint, or under what circumstances there are multiple hint
registers.

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llvm-reduce: Introduce new scoring mechanism for MIR reductions

Many MIR reductions benefit from or require increasing the instruction
count. For example, unlike in the IR, you may need to insert a

llvm-reduce: Introduce new scoring mechanism for MIR reductions

Many MIR reductions benefit from or require increasing the instruction
count. For example, unlike in the IR, you may need to insert a new
instruction to represent an undef. The current instruction reduction
pass works around this by sticking implicit defs on whatever
instruction happens to be first in the entry block block.

Other strategies I've applied manually include breaking instructions
with multiple defs into separate instructions, or breaking large
register defs into multiple subregister defs.

Make up a simple scoring system based on what I generally try to get
rid of first when manually reducing. Counts implicit defs as free
since reduction passes will be introducing them, although they
probably should count for something. It also might make more sense to
have a comparison the two functions, rather than having to compute a
contextless number. This isn't particularly well tested since overall
the MIR support isn't in a place where it is useful on the kinds of
testcases I want to throw at it.

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llvm-reduce: Fix incorrect cloning of MachineMemOperands

There were two problems with directly copying the MMOs from the old
function. The MMOs are owned by the function's Allocator, so need to
be r

llvm-reduce: Fix incorrect cloning of MachineMemOperands

There were two problems with directly copying the MMOs from the old
function. The MMOs are owned by the function's Allocator, so need to
be reallocated anyways (surprisingly I didn't notice breakage on
this). Second, the PseudoSourceValues are also allocated per function
and need to be reallocated.

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llvm-reduce: Fix crashing on file opening error for mir path

llvm-reduce: Support multiple MachineFunctions

The current testcase I'm trying to reduce only reproduces with IPRA
enabled and requires handling multiple functions.

The only real difference vs. the

llvm-reduce: Support multiple MachineFunctions

The current testcase I'm trying to reduce only reproduces with IPRA
enabled and requires handling multiple functions.

The only real difference vs. the IR is the extra indirect to look for
the underlying MachineFunction, so treat the ReduceWorkItem as the
module instead of the function.

The ugliest piece of this is really the ugliness of
MachineModuleInfo. It not only tracks actual module state, but has a
number of transient fields used for isel and/or the asm printer. These
shouldn't do any harm for the use here, though they should be
separated out.

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llvm-reduce: Try to parse triple/datalayout from module

This saves needing to specify -mtriple on nearly every use for MIR
reduction.

llvm-reduce: Fix not cloning MachineInstr flags

llvm-reduce: Simplify virtual register cloning

Just clone all the virtual registers instead of looking for def
operands. This preserves the register values used, simplifying the
rest of the code. Th

llvm-reduce: Simplify virtual register cloning

Just clone all the virtual registers instead of looking for def
operands. This preserves the register values used, simplifying the
rest of the code. This avoids needing to expose the register map to
target code.

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llvm-reduce: Preserve frame index values when cloning function

Previously the specific values used for fixed frame indexes was in
reverse order in the cloned function from the original, and a map wa

llvm-reduce: Preserve frame index values when cloning function

Previously the specific values used for fixed frame indexes was in
reverse order in the cloned function from the original, and a map was
used to adjust all frame indexes to the potentially new values. Insert
the fixed objects in reverse to avoid this. This simplifies other
code, since now we don't need to track down all frame indexes. This
will allow targets that store frame indexes in MachineFunctionInfo to
simply copy the values.

Note this isn't directly observable in the test since the resulting
MIR print/parse can shuffle the IDs around (in particular the final
serialization implicitly strips out dead objects).

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llvm-reduce: Fix cloning unset maxCallFrameSize

This was promoting an unset max call frame size to a max call frame
size of 0.

llvm-reduce: Clone properties of blocks

getSuccProbability was private for some reason, saying to go through
MachineBranchProbabilityInfo. There doesn't seem to be much point to
that, as that wrappe

llvm-reduce: Clone properties of blocks

getSuccProbability was private for some reason, saying to go through
MachineBranchProbabilityInfo. There doesn't seem to be much point to
that, as that wrapper directly calls this.

Like other areas, some of these fields aren't handled by the MIR
printer/parser so aren't tested.

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llvm-reduce: Clone some of the easy function properties

Error on some of these other fields, since tracking down test cases
for all of these at once is exhausting.

llvm-reduce: Handle cloning MachineFrameInfo and stack objects

This didn't work at all before, and would assert on any frame
index. Also copy the other fields, which I believe should cover
everythin

llvm-reduce: Handle cloning MachineFrameInfo and stack objects

This didn't work at all before, and would assert on any frame
index. Also copy the other fields, which I believe should cover
everything. There are a few that are untested since MIR serialization
is apparently still missing them (isStatepointSpillSlot,
ObjectSSPLayout, and ObjectSExt/ObjectZExt).

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llvm-reduce: Inform MRI of used phys reg masks

I'm not sure how to directly observe this invisible cache for a test.

llvm-reduce: Copy register allocation hints to clone

llvm-reduce: Fix asserting on undef virtual registers

This was only populating the virtual register map for def operands
that appeared in the function, but that may not exist if there are
only undef

llvm-reduce: Fix asserting on undef virtual registers

This was only populating the virtual register map for def operands
that appeared in the function, but that may not exist if there are
only undef uses.

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llvm-reduce: Fix handling of generic virtual registers

Try to preserve register banks, types and names. Fixes the lowest
hanging fruit in issue 54894.

Cleanup includes: LLVMAnalysis

Number of lines output by preprocessor:
before: 1065940348
after: 1065307662

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Diff

Cleanup includes: LLVMAnalysis

Number of lines output by preprocessor:
before: 1065940348
after: 1065307662

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D120659

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[llvm-reduce] Set ShouldPreserveUseListOrder=true

When exporting textual IR during reduction the ShouldPreserveUseListOrder
parameter of the IR printer should be set to get predictable results.

Dif

[llvm-reduce] Set ShouldPreserveUseListOrder=true

When exporting textual IR during reduction the ShouldPreserveUseListOrder
parameter of the IR printer should be set to get predictable results.

Differential Revision: https://reviews.llvm.org/D118585

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[llvm] Fix bugprone argument comments (NFC)

Identified with bugprone-argument-comment.