History log of /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/Utils.cpp (Results 1 – 25 of 115)
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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init
# 9e6d1f4b 17-Jul-2022 Kazu Hirata <[email protected]>

[CodeGen] Qualify auto variables in for loops (NFC)


Revision tags: llvmorg-14.0.6, llvmorg-14.0.5
# fb67d683 25-May-2022 serge-sans-paille <[email protected]>

[iwyu] Handle regressions in libLLVM header include

Running iwyu-diff on LLVM codebase since 7030654296a0416bd9402a0278 detected a few
regressions, fixing them.

Differential Revision: https://revie

[iwyu] Handle regressions in libLLVM header include

Running iwyu-diff on LLVM codebase since 7030654296a0416bd9402a0278 detected a few
regressions, fixing them.

Differential Revision: https://reviews.llvm.org/D126417

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Revision tags: llvmorg-14.0.4
# 485dd0b7 12-May-2022 Abinav Puthan Purayil <[email protected]>

[GlobalISel] Handle constant splat in funnel shift combine

This change adds the constant splat versions of m_ICst() (by using
getBuildVectorConstantSplat()) and uses it in
matchOrShiftToFunnelShift(

[GlobalISel] Handle constant splat in funnel shift combine

This change adds the constant splat versions of m_ICst() (by using
getBuildVectorConstantSplat()) and uses it in
matchOrShiftToFunnelShift(). The getBuildVectorConstantSplat() name is
shortened to getIConstantSplatVal() so that the *SExtVal() version would
have a more compact name.

Differential Revision: https://reviews.llvm.org/D125516

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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3
# 26e1ebd3 20-Jan-2022 Jay Foad <[email protected]>

[GlobalISel] Change ConstantFoldVectorBinop to return vector of APInt

Previously it built MIR for the results and returned a Register.

This avoids building constants for earlier elements of the vec

[GlobalISel] Change ConstantFoldVectorBinop to return vector of APInt

Previously it built MIR for the results and returned a Register.

This avoids building constants for earlier elements of the vector if
later elements will fail to fold, and allows CSEMIRBuilder::buildInstr
to avoid unconditionally building a copy from the result.

Use a new helper function MachineIRBuilder::buildBuildVectorConstant
to build a G_BUILD_VECTOR of G_CONSTANTs.

Differential Revision: https://reviews.llvm.org/D117758

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# 93977f37 05-Apr-2022 Daniel Sanders <[email protected]>

Check if register class was changed in constrainOperandRegClass()

NFC
When no actual change happens there's no need to notify the
observers about the fact the register class is being constrained.
So

Check if register class was changed in constrainOperandRegClass()

NFC
When no actual change happens there's no need to notify the
observers about the fact the register class is being constrained.
So we should avoid notifying observers when no change has
happened, because this can dramatically affect compile
time for particular test cases.

Reviewed By: dsanders, arsenm

Differential Revision: https://reviews.llvm.org/D122615

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# 60ca2569 23-Mar-2022 serge-sans-paille <[email protected]>

Cleanup include: Add missing header

Should fix https://lab.llvm.org/buildbot#builders/57/builds/16192 introduced by
02c28970b26b3888543d0a4c343a569fbf8fe16b


# 9a6e0afa 23-Mar-2022 Benjamin Kramer <[email protected]>

Unbreak the build after 02c28970b2


# 02c28970 21-Mar-2022 serge-sans-paille <[email protected]>

Cleanup include: codegen second round

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D122180


# ed98c1b3 09-Mar-2022 serge-sans-paille <[email protected]>

Cleanup includes: DebugInfo & CodeGen

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121332


# cb216076 15-Feb-2022 Mircea Trofin <[email protected]>

[nfc][codegen] Move RegisterBank[Info].h under CodeGen

This wraps up from D119053. The 2 headers are moved as described,
fixed file headers and include guards, updated all files where the old
paths

[nfc][codegen] Move RegisterBank[Info].h under CodeGen

This wraps up from D119053. The 2 headers are moved as described,
fixed file headers and include guards, updated all files where the old
paths were detected (simple grep through the repo), and `clang-format`-ed it all.

Differential Revision: https://reviews.llvm.org/D119876

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Revision tags: llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2
# 5af0f097 15-Aug-2020 Matt Arsenault <[email protected]>

GlobalISel: Constant fold G_PTR_ADD

Some globals lower to literal addresses on AMDGPU.

This may be wrong for non-integral address spaces. I'm wondering if we
should just allow regular G_ADD to use

GlobalISel: Constant fold G_PTR_ADD

Some globals lower to literal addresses on AMDGPU.

This may be wrong for non-integral address spaces. I'm wondering if we
should just allow regular G_ADD to use pointer types, and reserve
G_PTR_ADD for non-integral address spaces.

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# 930f2498 20-Mar-2021 Matt Arsenault <[email protected]>

GlobalISel: Constant fold integer min/max opcodes


# 0877fbcc 20-Mar-2021 Matt Arsenault <[email protected]>

GlobalISel: Add FoldBinOpIntoSelect combine

This will do the combine in cases that should fold, but don't
now. e.g. we're relying on the CSEMIRBuilder's incomplete constant
folding. For instance it

GlobalISel: Add FoldBinOpIntoSelect combine

This will do the combine in cases that should fold, but don't
now. e.g. we're relying on the CSEMIRBuilder's incomplete constant
folding. For instance it doesn't handle FP operations or vectors (and
we don't have separate constant folding combines either to catch
them).

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# 5599c431 18-Jan-2022 Matt Arsenault <[email protected]>

GlobalISel: Swap order of operand checks in ConstantFoldVectorBinop

Since constants are canonicalized to the RHS, this is more likely to
exit early.


# da728227 11-Jan-2022 Matt Arsenault <[email protected]>

GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors

This was ignoring the requested result register, resulting in a
missing def when this happened in the IRTranslator. Fixes some cra

GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors

This was ignoring the requested result register, resulting in a
missing def when this happened in the IRTranslator. Fixes some crashes
and verifier errors at -O0.

Alternatively we could pass DstOps to the constant fold functions.

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# 0ba4e4b5 09-Jan-2022 Matt Arsenault <[email protected]>

GlobalISel: Pass DebugLoc to getFunctionLiveInPhysReg

Fixes crash in assertion about dropping debug info.


# 29f88b93 23-Dec-2021 Petar Avramovic <[email protected]>

[GlobalISel] Rework more/fewer elements for vectors

Artifact combiner is not able to access individual elements after using
LCMTy style merge/unmerge, extract and insert to change vector number of
e

[GlobalISel] Rework more/fewer elements for vectors

Artifact combiner is not able to access individual elements after using
LCMTy style merge/unmerge, extract and insert to change vector number of
elements (pad with undef or split to sub-vector instructions).
Use unmerge to individual elements instead and then merge elements into
requested types.
Change argument lowering for vectors and moreElementsVector to use
buildPadVectorWithUndefElements and buildDeleteTrailingVectorElements.
FewerElementsVector had a few helpers that had different behavior,
introduce new helper for most of the opcodes.
FewerElementsVector helper is more flexible since it can create leftover
instruction smaller then requested type (useful in case target wants to
avoid pad with undef and use fewer registers). If target does not want
leftover of different type it should call more elements first.
Some helpers were performing more elements first to have split without
leftover. Opcodes that used this helper use clampMaxNumElementsStrict
(does more elements first) in LegalizerInfo to avoid test changes.
Fixes failures caused by failing to combine artifacts created during
more/fewer elements vector.

Differential Revision: https://reviews.llvm.org/D114198

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# f108c7f5 05-Dec-2021 Jack Andersen <[email protected]>

[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.

Expanding on D109750.

Since `DBG_VALUE` instructions have final register validity determined in
`LDVImpl::handleDebugValu

[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.

Expanding on D109750.

Since `DBG_VALUE` instructions have final register validity determined in
`LDVImpl::handleDebugValue`, there is no apparent reason to immediately prune
unused register operands as their defs are erased. Consequently, this renders
`MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval` moot; gaining a
substantial performance improvement.

The only necessary changes involve making relevant passes consider invalid
DBG_VALUE vregs uses as valid.

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D112852

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# bc5dbb0b 26-Nov-2021 Abinav Puthan Purayil <[email protected]>

[GlobalISel] Add matchers for constant splat.

This change exposes isBuildVectorConstantSplat() to the llvm namespace
and uses it to implement the constant splat versions of
m_SpecificICst().

Combin

[GlobalISel] Add matchers for constant splat.

This change exposes isBuildVectorConstantSplat() to the llvm namespace
and uses it to implement the constant splat versions of
m_SpecificICst().

CombinerHelper::matchOrShiftToFunnelShift() can now work with vector
types and CombinerHelper::matchMulOBy2()'s match for a constant splat is
simplified.

Differential Revision: https://reviews.llvm.org/D114625

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# bfd5dd15 25-Nov-2021 Kazu Hirata <[email protected]>

[llvm] Use range-based for loops (NFC)


# aa2d3b59 22-Oct-2021 Christudasan Devadasan <[email protected]>

GlobalISel/Utils: Use incoming regbank while constraining the superclasses

Register operands with superclasses can possibly have multiple regBanks
if they have different register types. The regBank

GlobalISel/Utils: Use incoming regbank while constraining the superclasses

Register operands with superclasses can possibly have multiple regBanks
if they have different register types. The regBank ambiguity resolved
during regbankselect should be used to constrain the operand regclass
instead of obtaining one from the MCInstrDesc.

This is a prerequisite patch for D109300 that introduces allocatable AV_*
Superclasses for AMDGPU by combining both VGPRs and AGPRs and we want to
restrain the regclass to either A or V based on the incoming regbank.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D112323

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# 5abce56e 11-Oct-2021 Amara Emerson <[email protected]>

[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.

Differential Revision: https://reviews.llvm.org/D111524


# 08b3c0d9 04-Oct-2021 Amara Emerson <[email protected]>

[GlobalISel] Combine G_UMULH x, (1 << c)) -> x >> (bitwidth - c)

In order to not generate an unnecessary G_CTLZ, I extended the constant folder
in the CSEMIRBuilder to handle G_CTLZ. I also added so

[GlobalISel] Combine G_UMULH x, (1 << c)) -> x >> (bitwidth - c)

In order to not generate an unnecessary G_CTLZ, I extended the constant folder
in the CSEMIRBuilder to handle G_CTLZ. I also added some extra handing of
vector constants too. It seems we don't have any support for doing constant
folding of vector constants, so the tests show some other useless G_SUB
instructions too.

Differential Revision: https://reviews.llvm.org/D111036

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# 8bfc0e06 29-Sep-2021 Amara Emerson <[email protected]>

[GlobalISel] Port the udiv -> mul by constant combine.

This is a straight port from the equivalent DAG combine.

Differential Revision: https://reviews.llvm.org/D110890


# 21661607 06-Oct-2021 Simon Pilgrim <[email protected]>

[llvm] Replace report_fatal_error(std::string) uses with report_fatal_error(Twine)

As described on D111049, we're trying to remove the <string> dependency from error handling and replace uses of rep

[llvm] Replace report_fatal_error(std::string) uses with report_fatal_error(Twine)

As described on D111049, we're trying to remove the <string> dependency from error handling and replace uses of report_fatal_error(const std::string&) with the Twine() variant which can be forward declared.

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