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Searched refs:Reg0 (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/
H A DTargetTest.cpp87 const unsigned Reg0 = Mips::T0; in TEST_F() local
88 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)), in TEST_F()
89 ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true))); in TEST_F()
99 const unsigned Reg0 = Mips::T0_64; in TEST_F() local
100 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)), in TEST_F()
101 ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false))); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNVOPDUtils.cpp69 Register Dst, Reg0, Reg1, Reg2; in checkVOPDRegConstraints() member
111 Comp.Reg0 = Op0.getReg(); in checkVOPDRegConstraints()
124 if (CInfo[0].Reg0 && CInfo[1].Reg0 && in checkVOPDRegConstraints()
125 CInfo[0].Reg0 % NumVGPRBanks == CInfo[1].Reg0 % NumVGPRBanks) in checkVOPDRegConstraints()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h122 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
126 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
128 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
130 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
132 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
138 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
140 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsSEFrameLowering.cpp462 unsigned Reg0 = in emitPrologue() local
468 std::swap(Reg0, Reg1); in emitPrologue()
471 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
480 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
484 std::swap(Reg0, Reg1); in emitPrologue()
487 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp175 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
188 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
196 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
219 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
237 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
248 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
251 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII() argument
[all …]
H A DMipsMCCodeEmitter.cpp96 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
101 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
102 if (Reg0 < Reg1) in LowerCompactBranch()
105 if (Reg0 >= Reg1) in LowerCompactBranch()
109 if (Reg1 >= Reg0) in LowerCompactBranch()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp233 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
234 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
238 if (Reg0.isVirtual()) { in runOnMachineFunction()
240 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
H A DHexagonBitTracker.cpp314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
845 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
847 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
849 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
851 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h755 uint16_t Reg0 = 0; variable
763 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
769 return Reg0;
774 return Reg0; in isValid()
780 Reg0 = Reg1;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2185 Ops.push_back(Reg0); in SelectVLD()
2371 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
2390 Ops.push_back(Reg0); in SelectVST()
2501 Ops.push_back(Reg0); in SelectVLDSTLane()
3048 Ops.push_back(Reg0); in SelectVLDDup()
3371 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
3382 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
3791 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
3795 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select()
3810 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
[all …]
H A DThumb2SizeReduction.cpp757 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
763 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
766 if (Reg0 != Reg2) { in ReduceTo2Addr()
769 if (Reg1 != Reg0) in ReduceTo2Addr()
776 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
781 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
788 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
H A DARMAsmPrinter.cpp322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
323 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp283 Register Reg0 = Op0.getReg(); in legalizeCustom() local
289 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
294 Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp223 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
246 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
261 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp291 Register Reg0; in TEST_F() local
294 m_GICmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1))); in TEST_F()
297 EXPECT_EQ(Copies[0], Reg0); in TEST_F()
316 Register Reg0; in TEST_F() local
319 m_GFCmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1))); in TEST_F()
322 EXPECT_EQ(Copies[0], Reg0); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp189 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() local
213 CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1)); in selectInlineAsm()
227 CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1)); in selectInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1436 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1439 printRegName(O, Reg0); in printVectorListTwo()
1449 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1452 printRegName(O, Reg0); in printVectorListTwoSpaced()
1504 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1507 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1551 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1554 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp463 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
467 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
497 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
510 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in ExpandMI()
H A DX86InstrInfo.cpp6172 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
6182 if ((HasDef && Reg0 == Reg1 && Tied1) || in foldMemoryOperandImpl()
6183 (HasDef && Reg0 == Reg2 && Tied2)) in foldMemoryOperandImpl()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp182 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
204 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
207 Reg0 = Reg2; in commuteInstructionImpl()
209 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
212 Reg0 = Reg1; in commuteInstructionImpl()
226 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
H A DRegisterCoalescer.cpp2633 Register Reg0; in valuesIdentical() local
2634 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2635 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2645 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2651 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
H A DRegAllocFast.cpp1218 Register Reg0 = MO0.getReg(); in allocateInstruction() local
1220 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in allocateInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp998 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1001 .addImm(Reg0) in InsertSEH()
1011 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1013 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1019 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
1049 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1052 .addImm(Reg0) in InsertSEH()
1060 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
1062 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1068 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1987 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in loadImmediate() local
1989 BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0); in loadImmediate()
1991 .addReg(Reg0).addImm(Value >> 32); in loadImmediate()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1171 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1181 if (Reg0 == Reg1) { in commuteInstructionImpl()
1201 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1204 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()