[MC] De-capitalize SwitchSection. NFC

Add SwitchSection to return switchSection. The API will be removed soon.

[MC] De-capitalize MCStreamer functions

Follow-up to c031378ce01b8485ba0ef486654bc9393c4ac024 .
The class is mostly consistent now.

[MIPS] Remove an incorrect microMIPS instruction alias

The microMIPS instruction set is compatible with the MIPS instruction
set at the assembly level but not in terms of encodings. `nop` in
microMI

[MIPS] Remove an incorrect microMIPS instruction alias

The microMIPS instruction set is compatible with the MIPS instruction
set at the assembly level but not in terms of encodings. `nop` in
microMIPS is a special case as it has the same encoding as `nop` for
MIPS.

Fix this error by reducing the usage of NOP in the MIPS backend such
that only that ISA correct variants are produced.

Differential Revision: https://reviews.llvm.org/D124716

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[MC] Fix letter case of some MCSection member functions

Cleanup LLVMMC headers

There's a few relevant forward declarations in there that may require downstream
adding explicit includes:

llvm/MC/MCContext.h no longer includes llvm/BinaryFormat/ELF.h, llv

Cleanup LLVMMC headers

There's a few relevant forward declarations in there that may require downstream
adding explicit includes:

llvm/MC/MCContext.h no longer includes llvm/BinaryFormat/ELF.h, llvm/MC/MCSubtargetInfo.h, llvm/MC/MCTargetOptions.h
llvm/MC/MCObjectStreamer.h no longer include llvm/MC/MCAssembler.h
llvm/MC/MCAssembler.h no longer includes llvm/MC/MCFixup.h, llvm/MC/MCFragment.h

Counting preprocessed lines required to rebuild llvm-project on my setup:
before: 1052436830
after: 1049293745

Which is significant and backs up the change in addition to the usual benefits of
decreasing coupling between headers and compilation units.

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D119244

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[MC] Add MCSubtargetInfo to MCAlignFragment

In preparation for passing the MCSubtargetInfo (STI) through to writeNops
so that it can use the STI in operation at the time, we need to record the
STI i

[MC] Add MCSubtargetInfo to MCAlignFragment

In preparation for passing the MCSubtargetInfo (STI) through to writeNops
so that it can use the STI in operation at the time, we need to record the
STI in operation when a MCAlignFragment may write nops as padding. The
STI is currently unused, a further patch will pass it through to
writeNops.

There are many places that can create an MCAlignFragment, in most cases
we can find out the STI in operation at the time. In a few places this
isn't possible as we are in initialisation or finalisation, or are
emitting constant pools. When possible I've tried to find the most
appropriate existing fragment to obtain the STI from, when none is
available use the per module STI.

For constant pools we don't actually need to use EmitCodeAlign as the
constant pools are data anyway so falling through into it via an
executable NOP is no better than falling through into data padding.

This is a prerequisite for D45962 which uses the STI to emit the
appropriate NOP for the STI. Which can differ per fragment.

Note that involves an interface change to InitSections. It is now
called initSections and requires a SubtargetInfo as a parameter.

Differential Revision: https://reviews.llvm.org/D45961

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[MC][ELF] Support for zero flag section groups

This change introduces support for zero flag ELF section groups to LLVM.
LLVM already supports COMDAT sections, which in ELF are a special type
of ELF

[MC][ELF] Support for zero flag section groups

This change introduces support for zero flag ELF section groups to LLVM.
LLVM already supports COMDAT sections, which in ELF are a special type
of ELF section groups. These are generally useful to enable linker GC
where you want a group of sections to always travel together, that is to
be either retained or discarded as a whole, but without the COMDAT
semantics. Other ELF assemblers already support zero flag ELF section
groups and this change helps us reach feature parity.

Differential Revision: https://reviews.llvm.org/D95851

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[mips] Implement .cpadd directive

This directive inserts code to add $gp to the argument's register when
support for position independent code is enabled.

For example, this code:
.cpadd $4
expand

[mips] Implement .cpadd directive

This directive inserts code to add $gp to the argument's register when
support for position independent code is enabled.

For example, this code:
.cpadd $4
expands to:
addu $4, $4, $gp

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[MIPS] Implement MIPS3D vector instructions

Patch by Michael Roe.

Differential Revision: https://reviews.llvm.org/D76247

[MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex}

[MC] De-capitalize another set of MCStreamer::Emit* functions

Emit{ValueTo,Code}Alignment Emit{DTP,TP,GP}* EmitSymbolValue etc

[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*

[mips] Fix sc, scs, ll, lld instructions expanding

There are a couple of bugs with the sc, scs, ll, lld instructions expanding:

1. On R6 these instruction pack immediate offset into a 9-bit field.

[mips] Fix sc, scs, ll, lld instructions expanding

There are a couple of bugs with the sc, scs, ll, lld instructions expanding:

1. On R6 these instruction pack immediate offset into a 9-bit field. Now
if an immediate exceeds 9-bits assembler does not perform expansion and
just rejects such instruction.

2. On 64-bit non-PIC code if an operand is a symbol assembler generates
incorrect sequence of instructions. It uses R_MIPS_HI16 and R_MIPS_LO16
relocations and skips R_MIPS_HIGHEST and R_MIPS_HIGHER ones.

To solve these problems this patch:
- Introduces `mem_simm9_exp` to mark 9-bit memory immediate operands
which require expansion. Probably later all `mem_simm9` operands will be
able to migrate on `mem_simm9_exp` and we rename it to `mem_simm9`.

- Adds new `OPERAND_MEM_SIMM9` operand type and assigns it to the
`mem_simm9_exp`. That allows to know operand size in the `processInstruction`
method and decide whether we need to expand instruction.

- Adds `expandMem9Inst` method to expand instructions with 9-bit memory
immediate operand. This method just load immediate into a "base"
register used by origibal instruction:

sc $2, 256($sp) => addiu $1, $sp, 256
sc $2, 0($1)

- Fix `expandMem16Inst` to support a correct set of relocations for
symbol loading in case of 64-bit non-PIC code.

ll $12, symbol => lui $12, 0
R_MIPS_HIGHEST symbol
daddiu $12, $12, 0
R_MIPS_HIGHER symbol
dsll $12, $12, 16
daddiu $12, $12, 0
R_MIPS_HI16 symbol
dsll $12, $12, 16
ll $12, 0($12)
R_MIPS_LO16 symbol

- Fix `expandMem16Inst` to unify handling of 3 and 4 operands
instructions.

- Delete unused now `MipsTargetStreamer::emitSCWithSymOffset` method.

Task for next patches - implement expanding for other instructions use
`mem_simm9` operand and other `mem_simm##` operands.

Differential Revision: https://reviews.llvm.org/D70648

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[Alignment][NFC] Remove unneeded llvm:: scoping on Align types

llvm-svn: 373081

[Alignment] Introduce llvm::Align to MCSection

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-J

[Alignment] Introduce llvm::Align to MCSection

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet, JDevlieghere

Subscribers: arsenm, sdardis, jvesely, nhaehnle, sbc100, hiraditya, aheejin, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67486

llvm-svn: 371831

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[mips] Inline emitStoreWithSymOffset and emitLoadWithSymOffset methods. NFC

Both methods `MipsTargetStreamer::emitStoreWithSymOffset` and
`MipsTargetStreamer::emitLoadWithSymOffset` are almost the s

[mips] Inline emitStoreWithSymOffset and emitLoadWithSymOffset methods. NFC

Both methods `MipsTargetStreamer::emitStoreWithSymOffset` and
`MipsTargetStreamer::emitLoadWithSymOffset` are almost the same and
differ argument names only. These methods are used in the single place
so it's better to inline their code and remove original methods.

llvm-svn: 370354

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[mips] Make a couple of class methods plain static functions. NFC

llvm-svn: 368162

[mips] Use isMicroMips() function to check enabled feature flag. NFC

llvm-svn: 368161

[Mips] Instruction `sc` now accepts symbol as an argument

Function MipsAsmParser::expandMemInst() did not properly handle
instruction `sc` with a symbol as an argument because first argument
would b

[Mips] Instruction `sc` now accepts symbol as an argument

Function MipsAsmParser::expandMemInst() did not properly handle
instruction `sc` with a symbol as an argument because first argument
would be counted twice. We add additional checks and handle this case
separately.

Patch by Mirko Brkusanin.

Differential Revision: https://reviews.llvm.org/D64252

llvm-svn: 368160

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[mips] Implement .cplocal directive

This directive forces to use the alternate register for context pointer.
For example, this code:
.cplocal $4
jal foo
expands to:
ld $25, %call16(foo)($4)

[mips] Implement .cplocal directive

This directive forces to use the alternate register for context pointer.
For example, this code:
.cplocal $4
jal foo
expands to:
ld $25, %call16(foo)($4)
jalr $25

Differential Revision: https://reviews.llvm.org/D64743

llvm-svn: 366300

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[Mips] Move InstPrinter files to MCTargetDesc. NFC

For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other target

[Mips] Move InstPrinter files to MCTargetDesc. NFC

For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.

llvm-svn: 360497

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[mips] Emit `.module softfloat` directive

This change fixes crash on an assertion in case of using
`soft float` ABI for mips32r6 target.

llvm-svn: 354882

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[mips][micrompis] Emit 16bit NOPs by default

Emit 16bit NOPs by default.
Use 32bit NOPs in delay slots where necessary.

Differential https://reviews.llvm.org/D55323

llvm-svn: 350733

[mips] Add support for Global INValidate ASE

This includes

Instructions: ginvi, ginvt,

Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv

Attribute: ginv

.MIPS.ab

[mips] Add support for Global INValidate ASE

This includes

Instructions: ginvi, ginvt,

Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv

Attribute: ginv

.MIPS.abiflags: GINV (0x20000)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D46268

llvm-svn: 332624

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