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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h41 MachineRegisterInfo &MRI,
46 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
66 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
77 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
86 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
132 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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H A DAMDGPURegisterBankInfo.cpp101 MachineRegisterInfo &MRI; member in __anonf9a34fae0111::ApplyRegBankMapping
175 MRI.setRegBank(Reg, *RB); in applyBank()
649 MRI->setRegBank(LoLHS, *Bank); in split64BitValueForMapping()
650 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
666 MRI.setType(Reg, NewTy); in setRegsToType()
686 LLT Ty = MRI.getType(Src); in buildReadFirstLane()
1184 LLT PtrTy = MRI.getType(Dst); in applyMappingDynStackAlloc()
1339 LLT Ty = MRI.getType(Dst); in applyMappingSBufferLoad()
1460 LLT Ty = MRI.getType(DstReg); in applyMappingBFE()
1635 MRI.setRegBank(Zero, in applyMappingMAD_64_32()
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H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
67 MachineRegisterInfo &MRI,
70 MachineRegisterInfo &MRI,
77 MachineRegisterInfo &MRI) const;
80 MachineRegisterInfo &MRI) const;
84 MachineRegisterInfo &MRI, int RSrcIdx) const;
145 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
151 unsigned getMappingType(const MachineRegisterInfo &MRI,
186 MachineRegisterInfo &MRI,
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H A DGCNRegPressure.cpp75 const auto RC = MRI.getRegClass(Reg); in getRegKind()
98 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
195 MRI.getMaxLaneMaskForVReg(MO.getReg()) : in getDefRegMask()
258 LiveMask = MRI.getMaxLaneMaskForVReg(Reg); in getLiveLaneMask()
282 MRI = &MF.getRegInfo(); in reset()
300 assert(MRI && "call reset first"); in recede()
328 LiveMask &= ~getDefRegMask(MO, *MRI); in recede()
356 assert(MRI && "call reset first"); in advanceBeforeNext()
403 LiveMask |= getDefRegMask(MO, *MRI); in advanceToNext()
470 printLivesAt(SI, LIS, *MRI); in isValid()
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H A DAMDGPUCombinerHelper.cpp126 if (!opMustUseVOP3Encoding(Use, MRI)) { in allUsesHaveSourceMods()
187 MatchInfo = MRI.getVRegDef(Src); in matchFoldableFneg()
193 if (MRI.hasOneNonDBGUse(Src)) { in matchFoldableFneg()
194 if (allUsesHaveSourceMods(MI, MRI, 0)) in matchFoldableFneg()
198 (allUsesHaveSourceMods(MI, MRI) || in matchFoldableFneg()
270 replaceRegOpWith(MRI, Op, Reg); in applyFoldableFneg()
278 replaceRegOpWith(MRI, X, XReg); in applyFoldableFneg()
280 replaceRegOpWith(MRI, Y, YReg); in applyFoldableFneg()
283 replaceRegOpWith(MRI, Y, YReg); in applyFoldableFneg()
361 if (MRI.hasOneNonDBGUse(MatchInfoDst)) { in applyFoldableFneg()
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H A DAMDGPUInstructionSelector.cpp68 MRI = &MF.getRegInfo(); in setupMF()
129 if (isVCC(DstReg, *MRI)) { in selectCOPY()
138 if (!isVCC(SrcReg, *MRI)) { in selectCOPY()
417 if (isVCC(Dst1Reg, *MRI)) { in selectG_UADDO_USUBO_UADDE_USUBE()
1107 if (!isVCC(CCReg, *MRI)) { in selectG_ICMP()
1140 if (isVCC(Dst, *MRI)) in selectIntrinsicIcmp()
1860 if (!isVCC(CCReg, *MRI)) { in selectG_SELECT()
1870 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2871 if (MRI->getType(DstReg) != V2S16 || MRI->getType(Src0Reg) != V2S16) in selectG_SHUFFLE_VECTOR()
3727 MachineRegisterInfo &MRI in selectVOP3PMods() local
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/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp202 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) in canReplaceReg()
207 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); in canReplaceReg()
433 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal()
442 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies()
449 auto SrcTy = MRI.getType(SrcReg); in getDefSrcRegIgnoringCopies()
452 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
735 MRI.setType(LiveIn, RegTy); in getFunctionLiveInPhysReg()
754 LLT Ty = MRI.getType(Op1); in ConstantFoldExtOp()
777 LLT Ty = MRI.getType(Src); in ConstantFoldCTLZ()
814 const LLT Ty = MRI.getType(Reg); in isKnownToBeAPowerOfTwo()
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H A DCombinerHelper.cpp74 auto &MRI = *MIB.getMRI(); in buildLogBase2() local
75 LLT Ty = MRI.getType(V); in buildLogBase2()
2338 isConstantOrConstantSplatVector(*MRI.getVRegDef(SelMI.getCondReg()), MRI); in matchConstantSelectCmp()
2571 if (MRI.hasOneUse(DstReg) && MRI.use_instr_begin(DstReg)->getOpcode() == in matchCombineInsertVecElts()
2648 if (!MRI.hasOneNonDBGUse(LHSReg) || !MRI.hasOneNonDBGUse(RHSReg)) in matchHoistLogicOpWithSameOpcodeHands()
2778 Dst, MRI, in matchOverlappingAnd()
3151 return isConstantOrConstantVector(*MRI.getVRegDef(OtherOperandReg), MRI, in matchFoldBinOpIntoSelect()
3241 if (!MRI.hasOneNonDBGUse(OrLHS) || !MRI.hasOneNonDBGUse(OrRHS)) in findCandidatesForLoadOrCombine()
3586 else if (MRI.getType(SrcVal) != MRI.getType(FoundSrcVal)) in getTruncStoreByteOffset()
4253 if (!mi_match(MI, MRI, in matchAndOrDisjointMask()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h89 Register constrainRegToClass(MachineRegisterInfo &MRI,
104 MachineRegisterInfo &MRI,
123 MachineRegisterInfo &MRI,
193 Register VReg, const MachineRegisterInfo &MRI,
215 const MachineRegisterInfo &MRI);
252 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef()
301 return isKnownNeverNaN(Val, MRI, true); in isKnownNeverSNaN()
414 const MachineRegisterInfo &MRI,
420 const MachineRegisterInfo &MRI,
444 const MachineRegisterInfo &MRI,
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H A DMIPatternMatch.h26 return P.match(MRI, R); in mi_match()
31 return P.match(MRI, &MI); in mi_match()
40 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
54 return MRI.hasOneNonDBGUse(Reg) && SubPat.match(MRI, Reg); in match()
69 return getIConstantVRegVal(Reg, MRI); in matchConstant()
270 return P.match(MRI, src) && And<Preds...>::match(MRI, src);
288 return P.match(MRI, src) || Or<Preds...>::match(MRI, src);
310 MI = MRI.getVRegDef(Reg);
324 Ty = MRI.getType(Reg);
616 if (!P.match(MRI, TmpPred))
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H A DLegalizationArtifactCombiner.h35 MachineRegisterInfo &MRI; variable
53 : Builder(B), MRI(MRI), LI(LI) {} in LegalizationArtifactCombiner()
70 if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) in tryCombineAnyExt()
83 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
126 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
131 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
185 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
189 LLT SrcTy = MRI.getType(SrcReg); in tryCombineSExt()
202 if (mi_match(SrcReg, MRI, in tryCombineSExt()
557 MachineRegisterInfo &MRI; variable
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp52 MachineRegisterInfo &MRI) { in IsRegInClass()
94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
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/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp223 match = mi_match(MIBAddCst, *MRI, in TEST_F()
230 match = mi_match(MIBAddCst, *MRI, in TEST_F()
234 match = mi_match(MIBAddCst, *MRI, in TEST_F()
239 match = mi_match(MIBCst, *MRI, in TEST_F()
242 match = mi_match(MIBUnmerge, *MRI, in TEST_F()
248 MIBAddCst, *MRI, in TEST_F()
255 MIBAddCst, *MRI, in TEST_F()
260 MIBAddCst, *MRI, in TEST_F()
267 MIBCst, *MRI, in TEST_F()
271 MIBUnmerge, *MRI, in TEST_F()
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H A DConstantFoldingTest.cpp85 MIBCst2.getReg(0), *MRI); in TEST_F()
90 MIBFCst2.getReg(0), *MRI); in TEST_F()
97 MIBCst2.getReg(0), *MRI); in TEST_F()
102 MIBFCst1.getReg(0), *MRI); in TEST_F()
109 MIBCst2.getReg(0), *MRI); in TEST_F()
114 MIBCst2.getReg(0), *MRI); in TEST_F()
121 MIBCst2.getReg(0), *MRI); in TEST_F()
126 MIBCst2.getReg(0), *MRI); in TEST_F()
133 MIBCst2.getReg(0), *MRI); in TEST_F()
145 MIBCst2.getReg(0), *MRI); in TEST_F()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anon133f2b0c0111::AArch64AdvSIMDScalar
145 MRI) && in getSrcFromCopy()
149 MRI) && in getSrcFromCopy()
151 MRI)) { in getSrcFromCopy()
208 if (!MRI->def_empty(OrigSrc0)) { in isProfitableToTransform()
210 MRI->def_instr_begin(OrigSrc0); in isProfitableToTransform()
221 if (!MRI->def_empty(OrigSrc1)) { in isProfitableToTransform()
223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform()
301 if (!MRI->def_empty(OrigSrc0)) { in transformInstruction()
320 if (!MRI->def_empty(OrigSrc1)) { in transformInstruction()
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H A DAArch64Combine.td17 [{ return matchFConstantToConstant(*${root}, MRI); }]),
60 [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
67 [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
74 [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
81 [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
88 [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
121 (apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
140 [{ return trySwapICmpOperands(*${root}, MRI); }]),
174 [{ return lowerVectorFCMP(*${root}, MRI, B); }]),
188 [{ return matchFoldMergeToZext(*${d}, MRI); }]),
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp360 return selectCopy(I, MRI); in select()
511 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
537 X86SelectAddress(*MRI.getVRegDef(I.getOperand(1).getReg()), MRI, AM); in selectLoadStoreOp()
571 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
624 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
643 LLT Ty = MRI.getType(DefReg); in selectConstant()
816 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
820 DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
911 LLT Ty = MRI.getType(LHS); in selectCmp()
988 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp681 auto &MRI = MF.getRegInfo(); in getImmedFromMO() local
1085 LLT Ty = MRI.getType(True); in emitSelect()
1150 if (mi_match(Reg, MRI, in emitSelect()
2295 Dst, MRI, in earlySelect()
4582 LLT Ty = MRI.getType(Dst); in emitCSetForFCmp()
4609 LLT Ty = MRI.getType(LHS); in emitFPCompare()
4820 auto &MRI = *MIB.getMRI(); in emitConditionalComparison() local
4853 auto &MRI = *MIB.getMRI(); in emitConjunctionRec() local
5089 if (isCMN(LHSDef, P, MRI)) in tryFoldIntegerCompare()
5102 if (isCMN(RHSDef, P, MRI)) in tryFoldIntegerCompare()
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H A DAArch64PostLegalizerCombiner.cpp54 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
79 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd()
82 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd()
125 MachineInstr &MI, MachineRegisterInfo &MRI, in matchAArch64MulConstCombine() argument
131 const LLT Ty = MRI.getType(LHS); in matchAArch64MulConstCombine()
156 if (MRI.hasOneNonDBGUse(LHS) && in matchAArch64MulConstCombine()
157 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
161 if (MRI.hasOneNonDBGUse(Dst)) { in matchAArch64MulConstCombine()
280 return MRI.getType(Dst).isScalar() && in matchMutateAnyExtToZExt()
281 mi_match(Src, MRI, in matchMutateAnyExtToZExt()
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H A DAArch64PostLegalizerLowering.cpp224 LLT Ty = MRI.getType(Dst); in matchREV()
327 MRI)) in matchDupFromInsertVectorElt()
479 MachineInstr *MI = MRI.getVRegDef(Reg); in isVShiftRImm()
522 const auto &Ty = MRI.getType(RHS); in tryAdjustICmpImmAndPred()
648 const LLT SrcTy = MRI.getType(Src1Reg); in matchDupLane()
750 if (!MRI.hasOneNonDBGUse(CmpOp)) in getCmpOperandFoldingProfit()
859 LLT DstTy = MRI.getType(LHS); in getVectorFCMP()
916 LLT DstTy = MRI.getType(Dst); in lowerVectorFCMP()
927 auto Splat = getAArch64VectorSplat(*MRI.getVRegDef(RHS), MRI); in lowerVectorFCMP()
950 MRI.replaceRegWith(Dst, CmpRes); in lowerVectorFCMP()
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H A DAArch64RegisterBankInfo.cpp527 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
545 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyUsesFP()
564 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyDefinesFP()
631 !MRI.getType(DstReg).isValid()) || in getInstrMapping()
633 !MRI.getType(SrcReg).isValid())) { in getInstrMapping()
683 LLT Ty = MRI.getType(MO.getReg()); in getInstrMapping()
701 LLT ScalarTy = MRI.getType(ScalarReg); in getInstrMapping()
706 onlyDefinesFP(*ScalarDef, MRI, TRI))) in getInstrMapping()
796 if (onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
846 onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
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H A DAArch64PreLegalizerCombiner.cpp74 LLT LHSTy = MRI.getType(LHS); in matchICmpRedundantTrunc()
82 !mi_match(RHS, MRI, m_SpecificICst(0))) in matchICmpRedundantTrunc()
85 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
100 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
151 UseInstr.getOperand(2).getReg(), MRI); in matchFoldGlobalOffset()
256 auto &MRI = *B.getMRI(); in tryToSimplifyUADDO() local
265 LLT WideTy0 = MRI.getType(Op0Wide); in tryToSimplifyUADDO()
266 LLT WideTy1 = MRI.getType(Op1Wide); in tryToSimplifyUADDO()
268 LLT OpTy = MRI.getType(ResVal); in tryToSimplifyUADDO()
289 if (!MRI.hasOneNonDBGUse(ResStatus)) in tryToSimplifyUADDO()
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp43 MachineRegisterInfo &MRI = MF.getRegInfo(); in addConstantsToTrack() local
183 if (!MRI.getRegClassOrNull(Reg)) in propagateSPIRVType()
198 MachineInstr *Def = MRI.getVRegDef(Reg); in insertAssignInstr()
203 Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg)); in insertAssignInstr()
205 MRI.setRegClass(NewReg, RC); in insertAssignInstr()
252 if (MRI.hasOneUse(Reg)) { in generateAssignInstrs()
311 if (MRI.getType(ValReg).isPointer()) { in createNewIdReg()
321 MRI.setRegClass(IdReg, DstClass); in createNewIdReg()
356 processInstr(MI, MIB, MRI, GR); in processInstrsWithTypeFolding()
370 if (MRI.getType(DstReg).isVector()) in processInstrsWithTypeFolding()
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/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp114 if (!MRI->getUniqueVRegDef(MO.getReg())) in checkADDrr()
171 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
179 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
183 if (!MRI->getUniqueVRegDef(I->getReg())) in processCandidate()
200 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
206 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg()
214 if (IsAma && MRI->getUniqueVRegDef(I->getReg())) in processDstReg()
215 processInst(MRI, I->getParent(), &*I, GVal); in processDstReg()
249 checkADDrr(MRI, RelocOp, GVal); in processInst()
260 MachineRegisterInfo *MRI = &MF->getRegInfo(); in removeLD() local
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
844 auto &MRI = MF.getRegInfo(); in select() local
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1034 return selectSelect(MIB, MRI); in select()
1038 return selectCmp(Helper, MIB, MRI); in select()
1057 return selectCmp(Helper, MIB, MRI); in select()
1077 return selectGlobal(MIB, MRI); in select()
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