Lines Matching refs:MRI
108 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI);
112 MachineRegisterInfo &MRI);
114 bool convertPtrAddToAdd(MachineInstr &I, MachineRegisterInfo &MRI);
117 MachineRegisterInfo &MRI) const;
119 MachineRegisterInfo &MRI) const;
135 MachineRegisterInfo &MRI);
137 bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI);
138 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI);
165 MachineRegisterInfo &MRI);
167 bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI);
169 MachineRegisterInfo &MRI);
172 bool tryOptBuildVecToSubregToReg(MachineInstr &MI, MachineRegisterInfo &MRI);
173 bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI);
174 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI);
175 bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI);
177 bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI);
178 bool selectExtractElt(MachineInstr &I, MachineRegisterInfo &MRI);
179 bool selectConcatVectors(MachineInstr &I, MachineRegisterInfo &MRI);
180 bool selectSplitVectorUnmerge(MachineInstr &I, MachineRegisterInfo &MRI);
190 MachineRegisterInfo &MRI);
191 bool selectIntrinsic(MachineInstr &I, MachineRegisterInfo &MRI);
192 bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI);
193 bool selectIntrinsicTrunc(MachineInstr &I, MachineRegisterInfo &MRI) const;
194 bool selectIntrinsicRound(MachineInstr &I, MachineRegisterInfo &MRI) const;
195 bool selectJumpTable(MachineInstr &I, MachineRegisterInfo &MRI);
196 bool selectBrJT(MachineInstr &I, MachineRegisterInfo &MRI);
197 bool selectTLSGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI);
198 bool selectReduction(MachineInstr &I, MachineRegisterInfo &MRI);
199 bool selectMOPS(MachineInstr &I, MachineRegisterInfo &MRI);
200 bool selectUSMovFromExtend(MachineInstr &I, MachineRegisterInfo &MRI);
360 MachineRegisterInfo &MRI) const;
370 const MachineRegisterInfo &MRI) const;
414 getExtendTypeForInst(MachineInstr &MI, MachineRegisterInfo &MRI,
681 auto &MRI = MF.getRegInfo(); in getImmedFromMO() local
689 getIConstantVRegValWithLookThrough(Root.getReg(), MRI, true); in getImmedFromMO()
706 const MachineRegisterInfo &MRI, in unsupportedBinOp() argument
708 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
731 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
859 static bool copySubReg(MachineInstr &I, MachineRegisterInfo &MRI, in copySubReg() argument
875 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
886 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in getRegClassesForCopy() argument
890 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
891 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in getRegClassesForCopy()
892 unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in getRegClassesForCopy()
893 unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in getRegClassesForCopy()
911 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
915 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
916 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
921 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI); in selectCopy()
925 << RBI.getSizeInBits(DstReg, MRI, TRI) << '\n'); in selectCopy()
950 copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg); in selectCopy()
957 copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg); in selectCopy()
965 Register PromoteReg = MRI.createVirtualRegister(PromotionRC); in selectCopy()
983 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
994 return selectCopy(I, TII, MRI, TRI, RBI); in selectCopy()
1081 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitSelect() local
1082 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1083 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1085 LLT Ty = MRI.getType(True); in emitSelect()
1092 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { in emitSelect()
1102 auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI, in emitSelect()
1116 if (mi_match(Reg, MRI, m_Neg(m_Reg(MatchReg)))) { in emitSelect()
1133 if (mi_match(Reg, MRI, m_Not(m_Reg(MatchReg)))) { in emitSelect()
1150 if (mi_match(Reg, MRI, in emitSelect()
1169 auto TryOptSelectCst = [&Opc, &True, &False, &CC, Is32Bit, &MRI, in emitSelect()
1173 auto TrueCst = getIConstantVRegValWithLookThrough(True, MRI); in emitSelect()
1174 auto FalseCst = getIConstantVRegValWithLookThrough(False, MRI); in emitSelect()
1361 MachineRegisterInfo &MRI) { in getTestBitReg() argument
1364 while (MachineInstr *MI = getDefIgnoringCopies(Reg, MRI)) { in getTestBitReg()
1368 !MRI.hasOneNonDBGUse(MI->getOperand(0).getReg())) in getTestBitReg()
1382 if (!NextReg.isValid() || !MRI.hasOneNonDBGUse(NextReg)) in getTestBitReg()
1400 auto VRegAndVal = getIConstantVRegValWithLookThrough(ConstantReg, MRI); in getTestBitReg()
1406 VRegAndVal = getIConstantVRegValWithLookThrough(ConstantReg, MRI); in getTestBitReg()
1421 getIConstantVRegValWithLookThrough(MI->getOperand(2).getReg(), MRI); in getTestBitReg()
1435 unsigned TestRegSize = MRI.getType(TestReg).getSizeInBits(); in getTestBitReg()
1497 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitTestBit() local
1500 TestReg = getTestBitReg(TestReg, Bit, IsNegative, MRI); in emitTestBit()
1501 LLT Ty = MRI.getType(TestReg); in emitTestBit()
1570 MachineRegisterInfo &MRI = *MIB.getMRI(); in emitCBZ() local
1571 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
1574 auto Ty = MRI.getType(CompareReg); in emitCBZ()
1617 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptCompareBranchFedByICmp() local
1625 auto VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI); in tryOptCompareBranchFedByICmp()
1626 MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
1639 uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; in tryOptCompareBranchFedByICmp()
1648 uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1; in tryOptCompareBranchFedByICmp()
1660 VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI); in tryOptCompareBranchFedByICmp()
1661 AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
1679 auto LHSTy = MRI.getType(LHS); in tryOptCompareBranchFedByICmp()
1710 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) { in selectCompareBranch() argument
1712 MachineInstr *CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1745 MachineRegisterInfo &MRI) { in getVectorShiftImm() argument
1746 assert(MRI.getType(Reg).isVector() && "Expected a *vector* shift operand"); in getVectorShiftImm()
1747 MachineInstr *OpMI = MRI.getVRegDef(Reg); in getVectorShiftImm()
1748 return getAArch64VectorSplatScalar(*OpMI, MRI); in getVectorShiftImm()
1753 static Optional<int64_t> getVectorSHLImm(LLT SrcTy, Register Reg, MachineRegisterInfo &MRI) { in getVectorSHLImm() argument
1754 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm()
1786 MachineRegisterInfo &MRI) { in selectVectorSHL() argument
1789 const LLT Ty = MRI.getType(DstReg); in selectVectorSHL()
1798 Optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI); in selectVectorSHL()
1831 MachineInstr &I, MachineRegisterInfo &MRI) { in selectVectorAshrLshr() argument
1835 const LLT Ty = MRI.getType(DstReg); in selectVectorAshrLshr()
1890 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const { in selectVaStartAAPCS()
1895 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const { in selectVaStartDarwin()
1899 Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectVaStartDarwin()
1925 MachineRegisterInfo &MRI = MF.getRegInfo(); in materializeLargeCMVal() local
1938 : MRI.createVirtualRegister(&AArch64::GPR64RegClass); in materializeLargeCMVal()
1961 MachineRegisterInfo &MRI = MF.getRegInfo(); in preISelLower() local
1965 bool Changed = contractCrossBankCopyIntoStore(I, MRI); in preISelLower()
1967 if (MRI.getType(SrcOp.getReg()).isPointer()) { in preISelLower()
1974 RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI); in preISelLower()
1980 return convertPtrAddToAdd(I, MRI); in preISelLower()
1987 const LLT DstTy = MRI.getType(DstReg); in preISelLower()
1990 MRI.setType(DstReg, LLT::scalar(64)); in preISelLower()
1995 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in preISelLower()
1999 MRI.setType(I.getOperand(0).getReg(), in preISelLower()
2001 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower()
2012 LLT SrcTy = MRI.getType(SrcReg); in preISelLower()
2013 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in preISelLower()
2017 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) { in preISelLower()
2040 MachineInstr &I, MachineRegisterInfo &MRI) { in convertPtrAddToAdd() argument
2044 const LLT PtrTy = MRI.getType(DstReg); in convertPtrAddToAdd()
2053 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID)); in convertPtrAddToAdd()
2055 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in convertPtrAddToAdd()
2060 MRI.setType(DstReg, CastPtrTy); in convertPtrAddToAdd()
2070 if (!mi_match(I.getOperand(2).getReg(), MRI, m_Neg(m_Reg(NegatedReg)))) in convertPtrAddToAdd()
2078 MachineRegisterInfo &MRI) { in earlySelectSHL() argument
2084 auto VRegAndVal = getIConstantVRegVal(MO.getReg(), MRI); in earlySelectSHL()
2088 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in earlySelectSHL()
2112 MachineInstr &I, MachineRegisterInfo &MRI) { in contractCrossBankCopyIntoStore() argument
2128 Register DefDstReg = getSrcRegIgnoringCopies(I.getOperand(0).getReg(), MRI); in contractCrossBankCopyIntoStore()
2131 LLT DefDstTy = MRI.getType(DefDstReg); in contractCrossBankCopyIntoStore()
2133 LLT StoreSrcTy = MRI.getType(StoreSrcReg); in contractCrossBankCopyIntoStore()
2144 if (RBI.getRegBank(StoreSrcReg, MRI, TRI) == in contractCrossBankCopyIntoStore()
2145 RBI.getRegBank(DefDstReg, MRI, TRI)) in contractCrossBankCopyIntoStore()
2159 MachineRegisterInfo &MRI = MF.getRegInfo(); in earlySelect() local
2166 auto ValAndVReg = getIConstantVRegValWithLookThrough(Src, MRI); in earlySelect()
2172 MRI.getType(Dst).getNumElements(), in earlySelect()
2173 ConstantInt::get(Type::getIntNTy(Ctx, MRI.getType(Src).getSizeInBits()), in earlySelect()
2175 if (!emitConstantVector(Dst, CV, MIB, MRI)) in earlySelect()
2183 if (selectUSMovFromExtend(I, MRI)) in earlySelect()
2189 return earlySelectSHL(I, MRI); in earlySelect()
2201 LLT Ty = MRI.getType(DefReg); in earlySelect()
2204 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
2207 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
2228 LLT Ty = MRI.getType(AddLHS); in earlySelect()
2237 if (!MRI.hasOneNonDBGUse(Reg)) in earlySelect()
2242 return getOpcodeDef(TargetOpcode::G_ICMP, Reg, MRI); in earlySelect()
2246 if (!mi_match(Reg, MRI, in earlySelect()
2249 auto *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, ZExt, MRI); in earlySelect()
2251 MRI.getType(Cmp->getOperand(2).getReg()).getSizeInBits() != 64) in earlySelect()
2281 LLT Ty = MRI.getType(Dst); in earlySelect()
2295 Dst, MRI, in earlySelect()
2331 MachineRegisterInfo &MRI = MF.getRegInfo(); in select() local
2352 const LLT DefTy = MRI.getType(DefReg); in select()
2355 MRI.getRegClassOrRegBank(DefReg); in select()
2374 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
2378 return selectCopy(I, TII, MRI, TRI, RBI); in select()
2409 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{}; in select()
2421 getIConstantVRegValWithLookThrough(I.getOperand(2).getReg(), MRI); in select()
2424 getIConstantVRegValWithLookThrough(I.getOperand(3).getReg(), MRI); in select()
2436 return selectCompareBranch(I, MF, MRI); in select()
2444 return selectBrJT(I, MRI); in select()
2451 MachineInstr *BaseMI = MRI.getVRegDef(I.getOperand(1).getReg()); in select()
2473 LLT DstTy = MRI.getType(DstReg); in select()
2519 const LLT DefTy = MRI.getType(DefReg); in select()
2521 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
2584 return RBI.constrainGenericRegister(DefReg, FPRRC, MRI); in select()
2592 MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
2598 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) { in select()
2624 LLT SrcTy = MRI.getType(SrcReg); in select()
2625 LLT DstTy = MRI.getType(DstReg); in select()
2642 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
2643 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select()
2674 DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); in select()
2679 AArch64::GPR32RegClass, MRI); in select()
2686 LLT SrcTy = MRI.getType(I.getOperand(2).getReg()); in select()
2687 LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in select()
2696 unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); in select()
2706 Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); in select()
2714 AArch64::GPR32RegClass, MRI); in select()
2738 return selectTLSGlobalValue(I, MRI); in select()
2767 LLT PtrTy = MRI.getType(LdSt.getPointerReg()); in select()
2801 if (MRI.getType(ValReg).getSizeInBits() == 64 && MemSizeInBits != 64) { in select()
2803 Register NewVal = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
2816 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2820 assert(MRI.getType(PtrReg).isPointer() && in select()
2825 const LLT ValTy = MRI.getType(ValReg); in select()
2826 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
2841 RBI.constrainGenericRegister(Copy, *RC, MRI); in select()
2854 MRI.createGenericVirtualRegister(LdSt.getMMO().getMemoryType()); in select()
2856 MRI.setRegBank(NewDst, RB); in select()
2863 auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB); in select()
2864 RBI.constrainGenericRegister(OldDst, *SubRegRC, MRI); in select()
2905 LoadStore->getOperand(0).getReg(), MRI); in select()
2923 if (MRI.getType(LoadStore->getOperand(0).getReg()).getSizeInBits() != 64) in select()
2927 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
2938 MRI); in select()
2946 if (unsupportedBinOp(I, RBI, MRI, TRI)) in select()
2950 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
2973 if (MRI.getType(I.getOperand(0).getReg()).isVector()) in select()
2974 return selectVectorAshrLshr(I, MRI); in select()
2978 MRI.getType(I.getOperand(0).getReg()).isVector()) in select()
2979 return selectVectorSHL(I, MRI); in select()
2988 const LLT ShiftTy = MRI.getType(ShiftReg); in select()
2989 const LLT SrcTy = MRI.getType(SrcReg); in select()
2996 MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); in select()
3003 if (unsupportedBinOp(I, RBI, MRI, TRI)) in select()
3009 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
3049 Optional<int64_t> MaskVal = getIConstantVRegSExtVal(MaskReg, MRI); in select()
3063 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in select()
3064 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); in select()
3069 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select()
3070 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
3087 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in select()
3088 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in select()
3131 return selectCopy(I, TII, MRI, TRI, RBI); in select()
3139 if (selectUSMovFromExtend(I, MRI)) in select()
3145 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI); in select()
3152 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
3159 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); in select()
3174 Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass); in select()
3182 return selectCopy(I, TII, MRI, TRI, RBI); in select()
3188 if (selectUSMovFromExtend(I, MRI)) in select()
3195 const LLT DstTy = MRI.getType(DefReg); in select()
3196 const LLT SrcTy = MRI.getType(SrcReg); in select()
3208 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() == in select()
3221 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); in select()
3223 RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID; in select()
3228 return selectCopy(I, TII, MRI, TRI, RBI); in select()
3240 MachineInstr *Def = MRI.getVRegDef(SrcReg); in select()
3246 Register OrDst = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
3258 MRI)) { in select()
3264 MRI)) { in select()
3278 MRI)) { in select()
3313 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()), in select()
3314 SrcTy = MRI.getType(I.getOperand(1).getReg()); in select()
3327 return selectCopy(I, TII, MRI, TRI, RBI); in select()
3332 return selectCopy(I, TII, MRI, TRI, RBI); in select()
3340 return selectCopy(I, TII, MRI, TRI, RBI); in select()
3353 Register DeadVReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
3364 return selectVectorICmp(I, MRI); in select()
3393 return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI) in select()
3394 : selectVaStartAAPCS(I, MF, MRI); in select()
3396 return selectIntrinsic(I, MRI); in select()
3398 return selectIntrinsicWithSideEffects(I, MRI); in select()
3401 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in select()
3403 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select()
3405 RBI.constrainGenericRegister(DstReg, *DstRC, MRI); in select()
3432 if (RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() != in select()
3435 LLT VecTy = MRI.getType(I.getOperand(0).getReg()); in select()
3449 return selectIntrinsicTrunc(I, MRI); in select()
3451 return selectIntrinsicRound(I, MRI); in select()
3453 return selectBuildVector(I, MRI); in select()
3455 return selectMergeValues(I, MRI); in select()
3457 return selectUnmergeValues(I, MRI); in select()
3459 return selectShuffleVector(I, MRI); in select()
3461 return selectExtractElt(I, MRI); in select()
3463 return selectInsertElt(I, MRI); in select()
3465 return selectConcatVectors(I, MRI); in select()
3467 return selectJumpTable(I, MRI); in select()
3470 return selectReduction(I, MRI); in select()
3476 return selectMOPS(I, MRI); in select()
3483 MachineRegisterInfo &MRI) { in selectReduction() argument
3485 LLT VecTy = MRI.getType(VecReg); in selectReduction()
3496 RBI.constrainGenericRegister(Copy, AArch64::FPR32RegClass, MRI); in selectReduction()
3535 MachineRegisterInfo &MRI) { in selectMOPS() argument
3556 const Register DstPtrCopy = MRI.cloneVirtualRegister(DstPtr.getReg()); in selectMOPS()
3557 const Register SrcValCopy = MRI.cloneVirtualRegister(SrcOrVal.getReg()); in selectMOPS()
3558 const Register SizeCopy = MRI.cloneVirtualRegister(Size.getReg()); in selectMOPS()
3565 RBI.constrainGenericRegister(DstPtrCopy, AArch64::GPR64commonRegClass, MRI); in selectMOPS()
3566 RBI.constrainGenericRegister(SrcValCopy, SrcValRegClass, MRI); in selectMOPS()
3567 RBI.constrainGenericRegister(SizeCopy, AArch64::GPR64RegClass, MRI); in selectMOPS()
3577 Register DefDstPtr = MRI.createVirtualRegister(&AArch64::GPR64commonRegClass); in selectMOPS()
3578 Register DefSize = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectMOPS()
3583 Register DefSrcPtr = MRI.createVirtualRegister(&SrcValRegClass); in selectMOPS()
3593 MachineRegisterInfo &MRI) { in selectBrJT() argument
3599 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT()
3600 Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in selectBrJT()
3613 MachineRegisterInfo &MRI) { in selectJumpTable() argument
3629 MachineInstr &I, MachineRegisterInfo &MRI) { in selectTLSGlobalValue() argument
3659 MRI); in selectTLSGlobalValue()
3665 MachineInstr &I, MachineRegisterInfo &MRI) const { in selectIntrinsicTrunc()
3666 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicTrunc()
3720 MachineInstr &I, MachineRegisterInfo &MRI) const { in selectIntrinsicRound()
3721 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicRound()
3775 MachineInstr &I, MachineRegisterInfo &MRI) { in selectVectorICmp() argument
3777 LLT DstTy = MRI.getType(DstReg); in selectVectorICmp()
3780 LLT SrcTy = MRI.getType(SrcReg); in selectVectorICmp()
3915 const RegisterBank &VecRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectVectorICmp()
3940 RBI.constrainGenericRegister(DstReg, *SrcRC, MRI); in selectVectorICmp()
3973 MachineInstr &I, MachineRegisterInfo &MRI) { in selectMergeValues() argument
3975 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in selectMergeValues()
3976 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); in selectMergeValues()
3978 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI); in selectMergeValues()
4012 Register SubToRegDef = MRI.createVirtualRegister(DstRC); in selectMergeValues()
4019 Register SubToRegDef2 = MRI.createVirtualRegister(DstRC); in selectMergeValues()
4073 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in emitExtractVectorElt() local
4089 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
4090 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
4101 DstReg = MRI.createVirtualRegister(DstRC); in emitExtractVectorElt()
4106 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI); in emitExtractVectorElt()
4126 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI); in emitExtractVectorElt()
4131 MachineInstr &I, MachineRegisterInfo &MRI) { in selectExtractElt() argument
4135 const LLT NarrowTy = MRI.getType(DstReg); in selectExtractElt()
4137 const LLT WideTy = MRI.getType(SrcReg); in selectExtractElt()
4147 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) { in selectExtractElt()
4153 auto VRegAndVal = getIConstantVRegValWithLookThrough(LaneIdxOp.getReg(), MRI); in selectExtractElt()
4159 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectExtractElt()
4170 MachineInstr &I, MachineRegisterInfo &MRI) { in selectSplitVectorUnmerge() argument
4173 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg()); in selectSplitVectorUnmerge()
4174 const LLT SrcTy = MRI.getType(SrcReg); in selectSplitVectorUnmerge()
4185 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI); in selectSplitVectorUnmerge()
4198 MachineRegisterInfo &MRI) { in selectUnmergeValues() argument
4203 if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() != in selectUnmergeValues()
4205 RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() != in selectUnmergeValues()
4216 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg()); in selectUnmergeValues()
4217 const LLT WideTy = MRI.getType(SrcReg); in selectUnmergeValues()
4225 return selectSplitVectorUnmerge(I, MRI); in selectUnmergeValues()
4253 *RBI.getRegBank(SrcReg, MRI, TRI)); in selectUnmergeValues()
4259 Register ImpDefReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass); in selectUnmergeValues()
4265 Register InsertReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass); in selectUnmergeValues()
4306 MRI.getRegClassOrNull(I.getOperand(1).getReg()); in selectUnmergeValues()
4312 RBI.constrainGenericRegister(CopyTo, *RC, MRI); in selectUnmergeValues()
4318 MachineInstr &I, MachineRegisterInfo &MRI) { in selectConcatVectors() argument
4452 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); in emitAddSub() local
4454 auto Ty = MRI.getType(LHS.getReg()); in emitAddSub()
4525 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); in emitCMN() local
4526 bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32); in emitCMN()
4528 return emitADDS(MRI.createVirtualRegister(RC), LHS, RHS, MIRBuilder); in emitCMN()
4535 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); in emitTST() local
4536 LLT Ty = MRI.getType(LHS.getReg()); in emitTST()
4544 if (auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS.getReg(), MRI)) { in emitTST()
4565 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); in emitIntegerCompare() local
4566 LLT CmpTy = MRI.getType(LHS.getReg()); in emitIntegerCompare()
4574 auto Dst = MRI.cloneVirtualRegister(LHS.getReg()); in emitIntegerCompare()
4580 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in emitCSetForFCmp() local
4582 LLT Ty = MRI.getType(Dst); in emitCSetForFCmp()
4594 Register Def1Reg = MRI.createVirtualRegister(RC); in emitCSetForFCmp()
4595 Register Def2Reg = MRI.createVirtualRegister(RC); in emitCSetForFCmp()
4608 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in emitFPCompare() local
4609 LLT Ty = MRI.getType(LHS); in emitFPCompare()
4618 const ConstantFP *FPImm = getConstantFPVRegVal(RHS, MRI); in emitFPCompare()
4627 const ConstantFP *LHSImm = getConstantFPVRegVal(LHS, MRI); in emitFPCompare()
4654 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); in emitVectorConcat() local
4656 const LLT Op1Ty = MRI.getType(Op1); in emitVectorConcat()
4657 const LLT Op2Ty = MRI.getType(Op2); in emitVectorConcat()
4677 const RegisterBank &FPRBank = *RBI.getRegBank(Op1, MRI, TRI); in emitVectorConcat()
4696 Dst = MRI.createVirtualRegister(DstRC); in emitVectorConcat()
4711 auto &MRI = *MIRBuilder.getMRI(); in emitCSINC() local
4712 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Dst); in emitCSINC()
4719 Size = MRI.getType(Dst).getSizeInBits(); in emitCSINC()
4763 bool WillNegate, MachineRegisterInfo &MRI, in canEmitConjunction() argument
4765 if (!MRI.hasOneNonDBGUse(Val)) in canEmitConjunction()
4767 MachineInstr *ValDef = MRI.getVRegDef(Val); in canEmitConjunction()
4783 if (!canEmitConjunction(O0, CanNegateL, MustBeFirstL, IsOR, MRI, Depth + 1)) in canEmitConjunction()
4787 if (!canEmitConjunction(O1, CanNegateR, MustBeFirstR, IsOR, MRI, Depth + 1)) in canEmitConjunction()
4820 auto &MRI = *MIB.getMRI(); in emitConditionalComparison() local
4821 LLT OpTy = MRI.getType(LHS); in emitConditionalComparison()
4853 auto &MRI = *MIB.getMRI(); in emitConjunctionRec() local
4854 MachineInstr *ValDef = MRI.getVRegDef(Val); in emitConjunctionRec()
4884 auto Dst = MRI.cloneVirtualRegister(LHS); in emitConjunctionRec()
4893 assert(MRI.hasOneNonDBGUse(Val) && "Valid conjunction/disjunction tree"); in emitConjunctionRec()
4900 bool ValidL = canEmitConjunction(LHS, CanNegateL, MustBeFirstL, IsOR, MRI); in emitConjunctionRec()
4907 bool ValidR = canEmitConjunction(RHS, CanNegateR, MustBeFirstR, IsOR, MRI); in emitConjunctionRec()
4986 MachineRegisterInfo &MRI = *MIB.getMRI(); in tryOptSelect() local
5005 MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg()); in tryOptSelect()
5009 if (!MRI.hasOneNonDBGUse(CondDefReg)) { in tryOptSelect()
5011 for (const MachineInstr &UI : MRI.use_nodbg_instructions(CondDefReg)) { in tryOptSelect()
5067 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in tryFoldIntegerCompare() local
5078 MachineInstr *LHSDef = getDefIgnoringCopies(LHS.getReg(), MRI); in tryFoldIntegerCompare()
5079 MachineInstr *RHSDef = getDefIgnoringCopies(RHS.getReg(), MRI); in tryFoldIntegerCompare()
5089 if (isCMN(LHSDef, P, MRI)) in tryFoldIntegerCompare()
5102 if (isCMN(RHSDef, P, MRI)) in tryFoldIntegerCompare()
5116 auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS.getReg(), MRI); in tryFoldIntegerCompare()
5128 MachineInstr &I, MachineRegisterInfo &MRI) { in selectShuffleVector() argument
5129 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in selectShuffleVector()
5131 const LLT Src1Ty = MRI.getType(Src1Reg); in selectShuffleVector()
5133 const LLT Src2Ty = MRI.getType(Src2Reg); in selectShuffleVector()
5190 RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI); in selectShuffleVector()
5212 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in emitLaneInsert() local
5216 DstReg = MRI.createVirtualRegister(DstRC); in emitLaneInsert()
5218 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
5238 MachineInstr &MI, MachineRegisterInfo &MRI) { in selectUSMovFromExtend() argument
5245 const LLT DstTy = MRI.getType(DefReg); in selectUSMovFromExtend()
5252 MI.getOperand(1).getReg(), MRI); in selectUSMovFromExtend()
5254 if (!Extract || !mi_match(Extract->getOperand(2).getReg(), MRI, m_ICst(Lane))) in selectUSMovFromExtend()
5258 const LLT &VecTy = MRI.getType(Src0); in selectUSMovFromExtend()
5287 Register NewReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in selectUSMovFromExtend()
5293 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in selectUSMovFromExtend()
5303 MachineRegisterInfo &MRI) { in selectInsertElt() argument
5308 const LLT DstTy = MRI.getType(DstReg); in selectInsertElt()
5313 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
5321 auto VRegAndVal = getIConstantVRegValWithLookThrough(IdxReg, MRI); in selectInsertElt()
5328 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
5351 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DemoteVec, MRI, TRI)); in selectInsertElt()
5366 RBI.constrainGenericRegister(DstReg, *RC, MRI); in selectInsertElt()
5380 MachineRegisterInfo &MRI) { in emitConstantVector() argument
5381 LLT DstTy = MRI.getType(Dst); in emitConstantVector()
5398 RBI.constrainGenericRegister(Dst, AArch64::FPR64RegClass, MRI); in emitConstantVector()
5411 Dst, *MRI.getRegClass(CPLoad->getOperand(0).getReg()), MRI); in emitConstantVector()
5416 MachineInstr &I, LLT DstTy, MachineRegisterInfo &MRI) { in tryOptConstantBuildVec() argument
5428 getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI); in tryOptConstantBuildVec()
5433 I.getOperand(Idx).getReg(), MRI))) in tryOptConstantBuildVec()
5440 if (!emitConstantVector(I.getOperand(0).getReg(), CV, MIB, MRI)) in tryOptConstantBuildVec()
5447 MachineInstr &I, MachineRegisterInfo &MRI) { in tryOptBuildVecToSubregToReg() argument
5454 LLT EltTy = MRI.getType(EltReg); in tryOptBuildVecToSubregToReg()
5457 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in tryOptBuildVecToSubregToReg()
5458 const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI); in tryOptBuildVecToSubregToReg()
5462 [&MRI](const MachineOperand &Op) { in tryOptBuildVecToSubregToReg()
5464 MRI); in tryOptBuildVecToSubregToReg()
5472 getRegClassForTypeOnBank(MRI.getType(Dst), DstRB); in tryOptBuildVecToSubregToReg()
5483 return RBI.constrainGenericRegister(Dst, *DstRC, MRI); in tryOptBuildVecToSubregToReg()
5487 MachineRegisterInfo &MRI) { in selectBuildVector() argument
5491 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); in selectBuildVector()
5492 const LLT EltTy = MRI.getType(I.getOperand(1).getReg()); in selectBuildVector()
5495 if (tryOptConstantBuildVec(I, DstTy, MRI)) in selectBuildVector()
5497 if (tryOptBuildVecToSubregToReg(I, MRI)) in selectBuildVector()
5502 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI); in selectBuildVector()
5530 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI)); in selectBuildVector()
5547 Register Reg = MRI.createVirtualRegister(RC); in selectBuildVector()
5553 RBI.constrainGenericRegister(DstReg, *RC, MRI); in selectBuildVector()
5572 auto &MRI = *MIB.getMRI(); in selectVectorLoadIntrinsic() local
5573 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in selectVectorLoadIntrinsic()
5579 assert(MRI.getType(Ptr).isPointer() && "Expected a pointer type?"); in selectVectorLoadIntrinsic()
5590 selectCopy(*Vec, TII, MRI, TRI, RBI); in selectVectorLoadIntrinsic()
5596 MachineInstr &I, MachineRegisterInfo &MRI) { in selectIntrinsicWithSideEffects() argument
5630 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicWithSideEffects()
5654 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in selectIntrinsicWithSideEffects()
5681 LLT Ty = MRI.getType(Src1); in selectIntrinsicWithSideEffects()
5731 Register SizeDef = MRI.createGenericVirtualRegister(LLT::scalar(64)); in selectIntrinsicWithSideEffects()
5746 MachineRegisterInfo &MRI) { in selectIntrinsic() argument
5757 if (MRI.getType(DstReg).getSizeInBits() != 32 || in selectIntrinsic()
5758 MRI.getType(SrcReg).getSizeInBits() != 32) in selectIntrinsic()
5763 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) { in selectIntrinsic()
5764 SrcReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass); in selectIntrinsic()
5769 AArch64::GPR32RegClass, MRI); in selectIntrinsic()
5772 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) in selectIntrinsic()
5773 DstReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass); in selectIntrinsic()
5785 AArch64::GPR32RegClass, MRI); in selectIntrinsic()
5796 auto DiscVal = getIConstantVRegVal(DiscReg, MRI); in selectIntrinsic()
5811 RBI.constrainGenericRegister(DiscReg, AArch64::GPR64spRegClass, MRI); in selectIntrinsic()
5814 RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI); in selectIntrinsic()
5825 RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI); in selectIntrinsic()
5851 Register NextFrame = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in selectIntrinsic()
5864 Register TmpReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectIntrinsic()
5990 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); in selectNegArithImmed() local
5991 if (MRI.getType(Root.getReg()).getSizeInBits() == 32) in selectNegArithImmed()
6007 MachineInstr &MI, const MachineRegisterInfo &MRI) const { in isWorthFoldingIntoExtendedReg()
6010 if (MRI.hasOneNonDBGUse(DefReg) || in isWorthFoldingIntoExtendedReg()
6022 return all_of(MRI.use_nodbg_instructions(DefReg), in isWorthFoldingIntoExtendedReg()
6044 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); in selectExtendedSHL() local
6045 MachineInstr *OffsetInst = MRI.getVRegDef(Offset.getReg()); in selectExtendedSHL()
6054 OffsetInst = MRI.getVRegDef(OffsetInst->getOperand(1).getReg()); in selectExtendedSHL()
6065 if (!isWorthFoldingIntoExtendedReg(*OffsetInst, MRI)) in selectExtendedSHL()
6073 auto ValAndVReg = getIConstantVRegValWithLookThrough(ConstantReg, MRI); in selectExtendedSHL()
6082 ValAndVReg = getIConstantVRegValWithLookThrough(ConstantReg, MRI); in selectExtendedSHL()
6114 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
6115 auto Ext = getExtendTypeForInst(*ExtInst, MRI, true); in selectExtendedSHL()
6127 MachineIRBuilder MIB(*MRI.getVRegDef(Root.getReg())); in selectExtendedSHL()
6156 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); in selectAddrModeShiftedExtendXReg() local
6171 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeShiftedExtendXReg()
6172 if (!PtrAdd || !isWorthFoldingIntoExtendedReg(*PtrAdd, MRI)) in selectAddrModeShiftedExtendXReg()
6178 getDefIgnoringCopies(PtrAdd->getOperand(2).getReg(), MRI); in selectAddrModeShiftedExtendXReg()
6195 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); in selectAddrModeRegisterOffset() local
6198 MachineInstr *Gep = MRI.getVRegDef(Root.getReg()); in selectAddrModeRegisterOffset()
6205 if (!MRI.hasOneNonDBGUse(Gep->getOperand(0).getReg())) in selectAddrModeRegisterOffset()
6228 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); in selectAddrModeXRO() local
6232 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeXRO()
6250 getIConstantVRegValWithLookThrough(PtrAdd->getOperand(2).getReg(), MRI); in selectAddrModeXRO()
6302 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); in selectAddrModeWRO() local
6305 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeWRO()
6306 if (!PtrAdd || !isWorthFoldingIntoExtendedReg(*PtrAdd, MRI)) in selectAddrModeWRO()
6311 MachineInstr *OffsetInst = getDefIgnoringCopies(RHS.getReg(), MRI); in selectAddrModeWRO()
6337 if (!isWorthFoldingIntoExtendedReg(*OffsetInst, MRI)) in selectAddrModeWRO()
6342 getExtendTypeForInst(*OffsetInst, MRI, /*IsLoadStore=*/true); in selectAddrModeWRO()
6369 MachineRegisterInfo &MRI = in selectAddrModeUnscaled() local
6375 if (!isBaseWithConstantOffset(Root, MRI)) in selectAddrModeUnscaled()
6378 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeUnscaled()
6383 MachineInstr *RHS = MRI.getVRegDef(OffImm.getReg()); in selectAddrModeUnscaled()
6408 MachineRegisterInfo &MRI) const { in tryFoldAddLowIntoImm()
6411 MachineInstr &Adrp = *MRI.getVRegDef(RootDef.getOperand(1).getReg()); in tryFoldAddLowIntoImm()
6446 MachineRegisterInfo &MRI = MF.getRegInfo(); in selectAddrModeIndexed() local
6451 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeIndexed()
6462 auto OpFns = tryFoldAddLowIntoImm(*RootDef, Size, MRI); in selectAddrModeIndexed()
6467 if (isBaseWithConstantOffset(Root, MRI)) { in selectAddrModeIndexed()
6470 MachineInstr *LHSDef = MRI.getVRegDef(LHS.getReg()); in selectAddrModeIndexed()
6471 MachineInstr *RHSDef = MRI.getVRegDef(RHS.getReg()); in selectAddrModeIndexed()
6524 MachineRegisterInfo &MRI = in selectShiftedRegister() local
6529 MachineInstr *ShiftInst = MRI.getVRegDef(Root.getReg()); in selectShiftedRegister()
6535 if (!isWorthFoldingIntoExtendedReg(*ShiftInst, MRI)) in selectShiftedRegister()
6549 unsigned NumBits = MRI.getType(ShiftReg).getSizeInBits(); in selectShiftedRegister()
6558 MachineInstr &MI, MachineRegisterInfo &MRI, bool IsLoadStore) const { in getExtendTypeForInst() argument
6565 Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in getExtendTypeForInst()
6582 unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in getExtendTypeForInst()
6619 MachineRegisterInfo &MRI = *MIB.getMRI(); in moveScalarRegClass() local
6620 auto Ty = MRI.getType(Reg); in moveScalarRegClass()
6628 selectCopy(*Copy, TII, MRI, TRI, RBI); in moveScalarRegClass()
6639 MachineRegisterInfo &MRI = in selectArithExtendedRegister() local
6645 MachineInstr *RootDef = getDefIgnoringCopies(Root.getReg(), MRI); in selectArithExtendedRegister()
6649 if (!isWorthFoldingIntoExtendedReg(*RootDef, MRI)) in selectArithExtendedRegister()
6664 MachineInstr *ExtDef = getDefIgnoringCopies(LHS.getReg(), MRI); in selectArithExtendedRegister()
6667 Ext = getExtendTypeForInst(*ExtDef, MRI); in selectArithExtendedRegister()
6673 Ext = getExtendTypeForInst(*RootDef, MRI); in selectArithExtendedRegister()
6682 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
6683 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
6703 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in renderTruncImm() local
6707 getIConstantVRegSExtVal(MI.getOperand(0).getReg(), MRI); in renderTruncImm()
6778 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in isDef32() local
6779 if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() != 32) in isDef32()
6800 static void fixupPHIOpBanks(MachineInstr &MI, MachineRegisterInfo &MRI, in fixupPHIOpBanks() argument
6804 const RegisterBank *DstRB = MRI.getRegBankOrNull(DstReg); in fixupPHIOpBanks()
6813 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg); in fixupPHIOpBanks()
6816 auto *OpDef = MRI.getVRegDef(OpReg); in fixupPHIOpBanks()
6817 const LLT &Ty = MRI.getType(OpReg); in fixupPHIOpBanks()
6827 MRI.setRegBank(Copy.getReg(0), *DstRB); in fixupPHIOpBanks()
6835 MachineRegisterInfo &MRI = MF.getRegInfo(); in processPHIs() local
6870 const LLT &Ty = MRI.getType(MO.getReg()); in processPHIs()
6875 const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg()); in processPHIs()
6887 fixupPHIOpBanks(*MI, MRI, RBI); in processPHIs()