Lines Matching refs:MRI
48 MachineRegisterInfo &MRI) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
186 MachineRegisterInfo &MRI, in guessRegClass() argument
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
192 const unsigned Size = MRI.getType(Reg).getSizeInBits(); in guessRegClass()
212 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
218 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
223 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
233 MachineRegisterInfo &MRI, in selectMergeValues() argument
242 assert(MRI.getType(VReg0).getSizeInBits() == 64 && in selectMergeValues()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
247 assert(MRI.getType(VReg1).getSizeInBits() == 32 && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
252 assert(MRI.getType(VReg2).getSizeInBits() == 32 && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
264 MachineRegisterInfo &MRI, in selectUnmergeValues() argument
274 assert(MRI.getType(VReg0).getSizeInBits() == 32 && in selectUnmergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
279 assert(MRI.getType(VReg1).getSizeInBits() == 32 && in selectUnmergeValues()
280 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
284 assert(MRI.getType(VReg2).getSizeInBits() == 64 && in selectUnmergeValues()
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
501 bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI, in validOpRegPair() argument
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
506 validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) && in validOpRegPair()
507 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID); in validOpRegPair()
510 bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg, in validReg() argument
513 if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) { in validReg()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
528 MachineRegisterInfo &MRI) const { in selectCmp()
532 if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID)) in selectCmp()
545 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize, in selectCmp()
550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp()
560 auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp()
610 MachineRegisterInfo &MRI) const { in selectGlobal()
627 LLT PtrTy = MRI.getType(MIB->getOperand(0).getReg()); in selectGlobal()
689 auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectGlobal()
719 auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectGlobal()
768 MachineRegisterInfo &MRI) const { in selectSelect()
775 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
844 auto &MRI = MF.getRegInfo(); in select() local
848 return selectCopy(I, TII, MRI, TRI, RBI); in select()
866 assert(MRI.getType(I.getOperand(0).getReg()).getSizeInBits() <= 32 && in select()
869 LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); in select()
881 Register AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass); in select()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
929 assert(MRI.getType(SrcReg).getSizeInBits() == 64 && "Unsupported size"); in select()
930 assert(MRI.getType(DstReg).getSizeInBits() <= 32 && "Unsupported size"); in select()
932 Register IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass); in select()
959 return selectCopy(I, TII, MRI, TRI, RBI); in select()
962 if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) { in select()
990 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits() / 8; in select()
1014 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1031 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1034 return selectSelect(MIB, MRI); in select()
1038 return selectCmp(Helper, MIB, MRI); in select()
1044 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
1057 return selectCmp(Helper, MIB, MRI); in select()
1077 return selectGlobal(MIB, MRI); in select()
1087 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select()
1089 LLT ValTy = MRI.getType(Reg); in select()
1108 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI)) in select()
1113 if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI)) in select()
1118 if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) { in select()
1146 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in select()
1147 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in select()