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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h51 MachineInstr *MI; member
171 bool tryCombineCopy(MachineInstr &MI);
172 bool matchCombineCopy(MachineInstr &MI);
173 void applyCombineCopy(MachineInstr &MI);
429 bool matchUndefStore(MachineInstr &MI);
480 bool eraseInst(MachineInstr &MI);
540 bool matchPtrAddZero(MachineInstr &MI);
541 void applyPtrAddZero(MachineInstr &MI);
580 MachineInstr &MI,
583 MachineInstr &MI,
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H A DLegalizerHelper.h363 LegalizeResult lowerLoad(GAnyLoad &MI);
364 LegalizeResult lowerStore(GStore &MI);
370 LegalizeResult lowerRotate(MachineInstr &MI);
373 LegalizeResult lowerUITOFP(MachineInstr &MI);
374 LegalizeResult lowerSITOFP(MachineInstr &MI);
375 LegalizeResult lowerFPTOUI(MachineInstr &MI);
376 LegalizeResult lowerFPTOSI(MachineInstr &MI);
380 LegalizeResult lowerFPOWI(MachineInstr &MI);
382 LegalizeResult lowerMinMax(MachineInstr &MI);
385 LegalizeResult lowerFMad(MachineInstr &MI);
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVInstPrinter.cpp43 printOperand(MI, i, O); in printRemainingVariableOps()
69 printInstruction(MI, Address, OS); in printInst()
72 printOpDecorate(MI, OS); in printInst()
74 recordOpExtInstImport(MI); in printInst()
76 printOpExtInst(MI, OS); in printInst()
251 if (OpNo < MI->getNumOperands()) { in printOperand()
306 if (OpNo < MI->getNumOperands()) { in printCapability()
315 if (OpNo < MI->getNumOperands()) { in printSourceLanguage()
324 if (OpNo < MI->getNumOperands()) { in printExecutionModel()
333 if (OpNo < MI->getNumOperands()) { in printAddressingModel()
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H A DSPIRVInstPrinter.h21 void recordOpExtInstImport(const MCInst *MI);
26 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
28 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
33 void printOpDecorate(const MCInst *MI, raw_ostream &O);
34 void printOpExtInst(const MCInst *MI, raw_ostream &O);
38 void printOpConstantVarOps(const MCInst *MI, unsigned StartIndex,
41 void printExtInst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
51 void printDim(const MCInst *MI, unsigned OpNo, raw_ostream &O);
53 void printSamplerAddressingMode(const MCInst *MI, unsigned OpNo,
59 void printImageChannelDataType(const MCInst *MI, unsigned OpNo,
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp71 MI.tieOperands(0, 1); in tieOpsIfNeeded()
134 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
137 tieOpsIfNeeded(MI); in shortenOn001()
147 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) in shortenOn001AddCC()
165 MI.removeOperand(3); in shortenFPConv()
166 MI.removeOperand(2); in shortenFPConv()
167 MI.removeOperand(1); in shortenFPConv()
170 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) in shortenFPConv()
197 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) in shortenFusedFPOp()
359 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) && in processBlock()
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/llvm-project-15.0.7/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kInstPrinter.h68 printAbsMem(MI, opNum, O); in printPCRelImm()
72 printARIMem(MI, opNum, O); in printARI8Mem()
75 printARIMem(MI, opNum, O); in printARI16Mem()
78 printARIMem(MI, opNum, O); in printARI32Mem()
102 printARIDMem(MI, opNum, O); in printARID8Mem()
122 printAbsMem(MI, opNum, O); in printAS8Mem()
125 printAbsMem(MI, opNum, O); in printAS16Mem()
128 printAbsMem(MI, opNum, O); in printAS32Mem()
132 printAbsMem(MI, opNum, O); in printAL8Mem()
135 printAbsMem(MI, opNum, O); in printAL16Mem()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp83 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
85 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
103 if (MI->allDefsAreDead()) { in LowerSubregToReg()
125 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, in LowerSubregToReg()
136 MBB->erase(MI); in LowerSubregToReg()
142 if (MI->allDefsAreDead()) { in LowerCopy()
155 << *MI); in LowerCopy()
166 MI->eraseFromParent(); in LowerCopy()
171 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), in LowerCopy()
180 MI->eraseFromParent(); in LowerCopy()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h72 const MachineInstr &MI,
79 const MachineInstr &MI,
230 bool PredicateInstruction(MachineInstr &MI,
370 bool isFloat(const MachineInstr &MI) const;
375 bool isJumpR(const MachineInstr &MI) const;
378 bool isLoopN(const MachineInstr &MI) const;
399 bool isSolo(const MachineInstr &MI) const;
401 bool isTC1(const MachineInstr &MI) const;
402 bool isTC2(const MachineInstr &MI) const;
404 bool isTC4x(const MachineInstr &MI) const;
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp262 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP)) in insertNoopsInBundle()
279 for (; MI != E && MI->isInsideBundle(); ++MI) { in processBundle()
1096 ((TII->isVOP3(MI) || TII->isSDWA(MI)) && MI.isCompare())) && in fixVcmpxPermlaneHazards()
1116 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVcmpxPermlaneHazards()
1164 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVMEMtoScalarWriteHazards()
1249 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixSMEMtoVectorWriteHazards()
1288 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVcmpxExecWARHazard()
1367 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixLdsBranchVmemWARHazard()
1443 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixLdsDirectVMEMHazard()
1592 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVALUPartialForwardingHazard()
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H A DSIMemoryLegalizer.cpp753 if (!(MI->mayLoad() && !MI->mayStore())) in getLoadInfo()
767 if (!(!MI->mayLoad() && MI->mayStore())) in getStoreInfo()
814 if (!(MI->mayLoad() && MI->mayStore())) in getAtomicCmpxchgOrRmwInfo()
908 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
925 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1247 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
1277 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1579 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1812 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
2079 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
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/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.h77 printSrcIdx(MI, OpNo, O); in printSrcIdx8()
80 printSrcIdx(MI, OpNo, O); in printSrcIdx16()
83 printSrcIdx(MI, OpNo, O); in printSrcIdx32()
86 printSrcIdx(MI, OpNo, O); in printSrcIdx64()
89 printDstIdx(MI, OpNo, O); in printDstIdx8()
92 printDstIdx(MI, OpNo, O); in printDstIdx16()
95 printDstIdx(MI, OpNo, O); in printDstIdx32()
98 printDstIdx(MI, OpNo, O); in printDstIdx64()
101 printMemOffset(MI, OpNo, O); in printMemOffs8()
104 printMemOffset(MI, OpNo, O); in printMemOffs16()
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H A DX86IntelInstPrinter.h88 printSrcIdx(MI, OpNo, O); in printSrcIdx8()
92 printSrcIdx(MI, OpNo, O); in printSrcIdx16()
96 printSrcIdx(MI, OpNo, O); in printSrcIdx32()
100 printSrcIdx(MI, OpNo, O); in printSrcIdx64()
104 printDstIdx(MI, OpNo, O); in printDstIdx8()
108 printDstIdx(MI, OpNo, O); in printDstIdx16()
112 printDstIdx(MI, OpNo, O); in printDstIdx32()
116 printDstIdx(MI, OpNo, O); in printDstIdx64()
120 printMemOffset(MI, OpNo, O); in printMemOffs8()
124 printMemOffset(MI, OpNo, O); in printMemOffs16()
[all …]
H A DX86InstComments.cpp287 unsigned NumOperands = MI->getNumOperands(); in printFMAComments()
306 switch (MI->getOpcode()) { in printFMAComments()
618 printMasking(OS, MI, MCII); in printFMAComments()
643 unsigned NumOperands = MI->getNumOperands(); in EmitAnyX86InstComments()
646 if (printFMAComments(MI, OS, MCII)) in EmitAnyX86InstComments()
649 switch (MI->getOpcode()) { in EmitAnyX86InstComments()
1268 if (MI->getOperand(2).isImm() && in EmitAnyX86InstComments()
1269 MI->getOperand(3).isImm()) in EmitAnyX86InstComments()
1278 if (MI->getOperand(3).isImm() && in EmitAnyX86InstComments()
1279 MI->getOperand(4).isImm()) in EmitAnyX86InstComments()
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/llvm-project-15.0.7/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp72 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
101 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
116 printOperand(MI, OpNum, STI, O); in printMemASOperandASX()
128 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
137 printOperand(MI, OpNum, STI, O); in printMemASOperandASX()
147 printOperand(MI, OpNum, STI, O); in printMemASOperandRRM()
159 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandRRM()
168 printOperand(MI, OpNum, STI, O); in printMemASOperandRRM()
178 printOperand(MI, OpNum, STI, O); in printMemASOperandHM()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h73 void printCPol(const MCInst *MI, unsigned OpNo,
91 void printLWE(const MCInst *MI, unsigned OpNo,
93 void printD16(const MCInst *MI, unsigned OpNo,
97 void printExpVM(const MCInst *MI, unsigned OpNo,
99 void printFORMAT(const MCInst *MI, unsigned OpNo,
101 void printSymbolicFormat(const MCInst *MI,
125 printOperand(MI, OpNum, STI, O); in printOperand()
141 void printFI(const MCInst *MI, unsigned OpNo,
154 void printOpSel(const MCInst *MI, unsigned OpNo,
158 void printNegLo(const MCInst *MI, unsigned OpNo,
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h83 return isDoLoopStart(MI) || isWhileLoopStart(MI); in isLoopStart()
109 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
116 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
127 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
132 MI->eraseFromParent();
137 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::tMOVr)) in RevertDoLoopStart()
142 MI->eraseFromParent(); in RevertDoLoopStart()
150 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
163 MI->eraseFromParent();
174 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
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/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h34 void printInstruction(const MCInst *MI, uint64_t Address,
55 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
57 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
119 printAdrLabelOperand<scale>(MI, OpNum, STI, O); in printAdrLabelOperand()
169 void printCPSIMod(const MCInst *MI, unsigned OpNum,
171 void printCPSIFlag(const MCInst *MI, unsigned OpNum,
214 void printPCLabel(const MCInst *MI, unsigned OpNum,
221 printThumbLdrLabelOperand(MI, OpNum, STI, O); in printThumbLdrLabelOperand()
223 void printFBits16(const MCInst *MI, unsigned OpNum,
225 void printFBits32(const MCInst *MI, unsigned OpNum,
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H A DARMInstPrinter.cpp95 unsigned Opcode = MI->getOpcode(); in printInst()
151 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
180 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
248 printRegisterList(MI, 3, STI, O); in printInst()
492 printOperand(MI, Op, STI, O); in printAddrMode2Operand()
565 printOperand(MI, Op, STI, O); in printAddrMode3Operand()
656 printOperand(MI, OpNum, STI, O); in printAddrMode5Operand()
680 printOperand(MI, OpNum, STI, O); in printAddrMode5FP16Operand()
1093 printOperand(MI, Op, STI, O); in printThumbAddrModeRROperand()
1115 printOperand(MI, Op, STI, O); in printThumbAddrModeImm5SOperand()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp81 switch (MI->getOpcode()) { in printInst()
91 printSaveRestore(MI, STI, O); in printInst()
96 printSaveRestore(MI, STI, O); in printInst()
101 printSaveRestore(MI, STI, O); in printInst()
106 printSaveRestore(MI, STI, O); in printInst()
117 switch (MI->getOpcode()) { in printInst()
189 printOperand(MI, opNum, STI, O); in printUImm()
201 switch (MI->getOpcode()) { in printMemOperand()
216 printOperand(MI, opNum, STI, O); in printMemOperand()
269 switch (MI.getOpcode()) { in printAlias()
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp42 printOperand(MI, OpNo0, OS); in printInst()
44 printOperand(MI, OpNo1, OS); in printInst()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
75 if (isPreIncrementForm(MI, AddOffset)) { in printMemoryLoadIncrement()
81 if (isPostIncrementForm(MI, AddOffset)) { in printMemoryLoadIncrement()
83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
94 if (isPreIncrementForm(MI, AddOffset)) { in printMemoryStoreIncrement()
103 << decIncOperator(MI) << "]"; in printMemoryStoreIncrement()
110 switch (MI->getOpcode()) { in printAlias()
144 if (!printAlias(MI, OS) && !printAliasInstr(MI, Address, OS)) in printInst()
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/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCBranchFinalize.cpp118 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in replaceWithBRcc()
122 .add(MI->getOperand(2)) in replaceWithBRcc()
124 MI->eraseFromParent(); in replaceWithBRcc()
126 replaceWithCmpBcc(MI); in replaceWithBRcc()
133 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in replaceWithCmpBcc()
136 .add(MI->getOperand(2)); in replaceWithCmpBcc()
137 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc)) in replaceWithCmpBcc()
140 MI->eraseFromParent(); in replaceWithCmpBcc()
156 for (auto &MI : MBB) { in runOnMachineFunction() local
163 if (MI.isBranch()) { in runOnMachineFunction()
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp90 MI->eraseFromParent(); in addConstantsToTrack()
93 MI->eraseFromParent(); in addConstantsToTrack()
129 MIB.setInsertPt(*MI.getParent(), MI); in insertBitcasts()
130 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
157 MIB.setInsertPt(*MI->getParent(), MI); in propagateSPIRVType()
163 MIB.setInsertPt(*MI->getParent(), MI); in propagateSPIRVType()
276 MI.getNumExplicitOperands() - MI.getNumExplicitDefs(); in generateAssignInstrs()
328 assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg())); in processInstr()
335 (MI.getNextNode() ? MI.getNextNode()->getIterator() in processInstr()
415 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isPredicate() && in processSwitches()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp103 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getVSRpEvenEncoding()
156 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
174 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
192 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; in getMemRIX16Encoding()
241 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34; in getMemRI34PCRelEncoding()
322 uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) in getMemRI34Encoding()
335 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE8DisEncoding()
410 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || in get_crbitm_encoding()
411 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && in get_crbitm_encoding()
437 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && in getMachineOpValue()
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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.cpp73 printInstruction(MI, Address, O); in printInst()
93 printUImmOperand<1>(MI, OpNum, O); in printU1ImmOperand()
98 printUImmOperand<2>(MI, OpNum, O); in printU2ImmOperand()
103 printUImmOperand<3>(MI, OpNum, O); in printU3ImmOperand()
108 printUImmOperand<4>(MI, OpNum, O); in printU4ImmOperand()
113 printUImmOperand<6>(MI, OpNum, O); in printU6ImmOperand()
118 printSImmOperand<8>(MI, OpNum, O); in printS8ImmOperand()
170 printPCRelOperand(MI, OpNum, O); in printPCRelTLSOperand()
197 printAddress(&MAI, MI->getOperand(OpNum).getReg(), MI->getOperand(OpNum + 1), in printBDAddrOperand()
203 printAddress(&MAI, MI->getOperand(OpNum).getReg(), MI->getOperand(OpNum + 1), in printBDXAddrOperand()
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H A DSystemZMCCodeEmitter.cpp207 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr12Encoding()
217 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr20Encoding()
227 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr12Encoding()
229 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); in getBDXAddr12Encoding()
238 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr20Encoding()
240 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); in getBDXAddr20Encoding()
250 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDLAddr12Len4Encoding()
261 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDLAddr12Len8Encoding()
272 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDRAddr12Encoding()
274 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); in getBDRAddr12Encoding()
[all …]

12345678910>>...50