Lines Matching refs:MI
217 void reportUnsupported(const MachineBasicBlock::iterator &MI,
233 const MachineBasicBlock::iterator &MI) const;
242 const MachineBasicBlock::iterator &MI) const;
246 const MachineBasicBlock::iterator &MI) const;
251 const MachineBasicBlock::iterator &MI) const;
256 const MachineBasicBlock::iterator &MI) const;
277 bool enableNamedBit(const MachineBasicBlock::iterator MI,
288 virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
295 virtual bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
302 virtual bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
309 virtual bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
321 virtual bool insertWait(MachineBasicBlock::iterator &MI,
333 virtual bool insertAcquire(MachineBasicBlock::iterator &MI,
344 virtual bool insertRelease(MachineBasicBlock::iterator &MI,
360 bool enableGLCBit(const MachineBasicBlock::iterator &MI) const { in enableGLCBit()
361 return enableNamedBit(MI, AMDGPU::CPol::GLC); in enableGLCBit()
366 bool enableSLCBit(const MachineBasicBlock::iterator &MI) const { in enableSLCBit()
367 return enableNamedBit(MI, AMDGPU::CPol::SLC); in enableSLCBit()
374 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
378 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
382 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
386 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
391 bool insertWait(MachineBasicBlock::iterator &MI,
398 bool insertAcquire(MachineBasicBlock::iterator &MI,
403 bool insertRelease(MachineBasicBlock::iterator &MI,
415 bool insertAcquire(MachineBasicBlock::iterator &MI,
427 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
431 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
435 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
439 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
444 bool insertWait(MachineBasicBlock::iterator &MI,
451 bool insertAcquire(MachineBasicBlock::iterator &MI,
456 bool insertRelease(MachineBasicBlock::iterator &MI,
468 bool enableSC0Bit(const MachineBasicBlock::iterator &MI) const { in enableSC0Bit()
469 return enableNamedBit(MI, AMDGPU::CPol::SC0); in enableSC0Bit()
474 bool enableSC1Bit(const MachineBasicBlock::iterator &MI) const { in enableSC1Bit()
475 return enableNamedBit(MI, AMDGPU::CPol::SC1); in enableSC1Bit()
480 bool enableNTBit(const MachineBasicBlock::iterator &MI) const { in enableNTBit()
481 return enableNamedBit(MI, AMDGPU::CPol::NT); in enableNTBit()
488 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
492 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
496 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
500 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
505 bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
508 bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
518 bool enableDLCBit(const MachineBasicBlock::iterator &MI) const { in enableDLCBit()
519 return enableNamedBit(MI, AMDGPU::CPol::DLC); in enableDLCBit()
526 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
530 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
535 bool insertWait(MachineBasicBlock::iterator &MI,
542 bool insertAcquire(MachineBasicBlock::iterator &MI,
552 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
556 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
573 bool isAtomicRet(const MachineInstr &MI) const { in isAtomicRet()
574 return SIInstrInfo::isAtomicRet(MI); in isAtomicRet()
584 MachineBasicBlock::iterator &MI);
588 MachineBasicBlock::iterator &MI);
592 MachineBasicBlock::iterator &MI);
596 MachineBasicBlock::iterator &MI);
617 void SIMemOpAccess::reportUnsupported(const MachineBasicBlock::iterator &MI, in reportUnsupported() argument
619 const Function &Func = MI->getParent()->getParent()->getFunction(); in reportUnsupported()
620 DiagnosticInfoUnsupported Diag(Func, Msg, MI->getDebugLoc()); in reportUnsupported()
690 const MachineBasicBlock::iterator &MI) const { in constructFromMIWithMMO()
691 assert(MI->getNumMemOperands() > 0); in constructFromMIWithMMO()
702 for (const auto &MMO : MI->memoperands()) { in constructFromMIWithMMO()
712 reportUnsupported(MI, in constructFromMIWithMMO()
732 reportUnsupported(MI, "Unsupported atomic synchronization scope"); in constructFromMIWithMMO()
740 reportUnsupported(MI, "Unsupported atomic address space"); in constructFromMIWithMMO()
750 const MachineBasicBlock::iterator &MI) const { in getLoadInfo()
751 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getLoadInfo()
753 if (!(MI->mayLoad() && !MI->mayStore())) in getLoadInfo()
757 if (MI->getNumMemOperands() == 0) in getLoadInfo()
760 return constructFromMIWithMMO(MI); in getLoadInfo()
764 const MachineBasicBlock::iterator &MI) const { in getStoreInfo()
765 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getStoreInfo()
767 if (!(!MI->mayLoad() && MI->mayStore())) in getStoreInfo()
771 if (MI->getNumMemOperands() == 0) in getStoreInfo()
774 return constructFromMIWithMMO(MI); in getStoreInfo()
778 const MachineBasicBlock::iterator &MI) const { in getAtomicFenceInfo()
779 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getAtomicFenceInfo()
781 if (MI->getOpcode() != AMDGPU::ATOMIC_FENCE) in getAtomicFenceInfo()
785 static_cast<AtomicOrdering>(MI->getOperand(0).getImm()); in getAtomicFenceInfo()
787 SyncScope::ID SSID = static_cast<SyncScope::ID>(MI->getOperand(1).getImm()); in getAtomicFenceInfo()
790 reportUnsupported(MI, "Unsupported atomic synchronization scope"); in getAtomicFenceInfo()
802 reportUnsupported(MI, "Unsupported atomic address space"); in getAtomicFenceInfo()
811 const MachineBasicBlock::iterator &MI) const { in getAtomicCmpxchgOrRmwInfo()
812 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getAtomicCmpxchgOrRmwInfo()
814 if (!(MI->mayLoad() && MI->mayStore())) in getAtomicCmpxchgOrRmwInfo()
818 if (MI->getNumMemOperands() == 0) in getAtomicCmpxchgOrRmwInfo()
821 return constructFromMIWithMMO(MI); in getAtomicCmpxchgOrRmwInfo()
830 bool SICacheControl::enableNamedBit(const MachineBasicBlock::iterator MI, in enableNamedBit() argument
832 MachineOperand *CPol = TII->getNamedOperand(*MI, AMDGPU::OpName::cpol); in enableNamedBit()
857 const MachineBasicBlock::iterator &MI, in enableLoadCacheBypass() argument
860 assert(MI->mayLoad() && !MI->mayStore()); in enableLoadCacheBypass()
869 Changed |= enableGLCBit(MI); in enableLoadCacheBypass()
892 const MachineBasicBlock::iterator &MI, in enableStoreCacheBypass() argument
895 assert(!MI->mayLoad() && MI->mayStore()); in enableStoreCacheBypass()
905 const MachineBasicBlock::iterator &MI, in enableRMWCacheBypass() argument
908 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
920 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal() argument
925 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
940 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
947 Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false, in enableVolatileAndOrNonTemporal()
956 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
957 Changed |= enableSLCBit(MI); in enableVolatileAndOrNonTemporal()
964 bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI, in insertWait() argument
972 MachineBasicBlock &MBB = *MI->getParent(); in insertWait()
973 DebugLoc DL = MI->getDebugLoc(); in insertWait()
976 ++MI; in insertWait()
1051 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate); in insertWait()
1056 --MI; in insertWait()
1061 bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire() argument
1070 MachineBasicBlock &MBB = *MI->getParent(); in insertAcquire()
1071 DebugLoc DL = MI->getDebugLoc(); in insertAcquire()
1074 ++MI; in insertAcquire()
1080 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_WBINVL1)); in insertAcquire()
1101 --MI; in insertAcquire()
1106 bool SIGfx6CacheControl::insertRelease(MachineBasicBlock::iterator &MI, in insertRelease() argument
1111 return insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE, in insertRelease()
1115 bool SIGfx7CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire() argument
1124 MachineBasicBlock &MBB = *MI->getParent(); in insertAcquire()
1125 DebugLoc DL = MI->getDebugLoc(); in insertAcquire()
1134 ++MI; in insertAcquire()
1140 BuildMI(MBB, MI, DL, TII->get(InvalidateL1)); in insertAcquire()
1161 --MI; in insertAcquire()
1167 const MachineBasicBlock::iterator &MI, in enableLoadCacheBypass() argument
1170 assert(MI->mayLoad() && !MI->mayStore()); in enableLoadCacheBypass()
1179 Changed |= enableGLCBit(MI); in enableLoadCacheBypass()
1187 Changed |= enableGLCBit(MI); in enableLoadCacheBypass()
1209 const MachineBasicBlock::iterator &MI, in enableStoreCacheBypass() argument
1212 assert(!MI->mayLoad() && MI->mayStore()); in enableStoreCacheBypass()
1244 const MachineBasicBlock::iterator &MI, in enableRMWCacheBypass() argument
1247 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
1272 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal() argument
1277 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1292 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
1299 Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false, in enableVolatileAndOrNonTemporal()
1308 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
1309 Changed |= enableSLCBit(MI); in enableVolatileAndOrNonTemporal()
1316 bool SIGfx90ACacheControl::insertWait(MachineBasicBlock::iterator &MI, in insertWait() argument
1340 return SIGfx7CacheControl::insertWait(MI, Scope, AddrSpace, Op, in insertWait()
1344 bool SIGfx90ACacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire() argument
1353 MachineBasicBlock &MBB = *MI->getParent(); in insertAcquire()
1354 DebugLoc DL = MI->getDebugLoc(); in insertAcquire()
1357 ++MI; in insertAcquire()
1365 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_INVL2)); in insertAcquire()
1403 --MI; in insertAcquire()
1405 Changed |= SIGfx7CacheControl::insertAcquire(MI, Scope, AddrSpace, Pos); in insertAcquire()
1410 bool SIGfx90ACacheControl::insertRelease(MachineBasicBlock::iterator &MI, in insertRelease() argument
1417 MachineBasicBlock &MBB = *MI->getParent(); in insertRelease()
1418 DebugLoc DL = MI->getDebugLoc(); in insertRelease()
1421 ++MI; in insertRelease()
1432 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_WBL2)) in insertRelease()
1451 --MI; in insertRelease()
1454 SIGfx7CacheControl::insertRelease(MI, Scope, AddrSpace, in insertRelease()
1461 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope, in enableLoadCacheBypass() argument
1463 assert(MI->mayLoad() && !MI->mayStore()); in enableLoadCacheBypass()
1470 Changed |= enableSC0Bit(MI); in enableLoadCacheBypass()
1471 Changed |= enableSC1Bit(MI); in enableLoadCacheBypass()
1475 Changed |= enableSC1Bit(MI); in enableLoadCacheBypass()
1483 Changed |= enableSC0Bit(MI); in enableLoadCacheBypass()
1505 const MachineBasicBlock::iterator &MI, in enableStoreCacheBypass() argument
1507 assert(!MI->mayLoad() && MI->mayStore()); in enableStoreCacheBypass()
1514 Changed |= enableSC0Bit(MI); in enableStoreCacheBypass()
1515 Changed |= enableSC1Bit(MI); in enableStoreCacheBypass()
1519 Changed |= enableSC1Bit(MI); in enableStoreCacheBypass()
1523 Changed |= enableSC0Bit(MI); in enableStoreCacheBypass()
1545 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope, in enableRMWCacheBypass() argument
1547 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
1554 Changed |= enableSC1Bit(MI); in enableRMWCacheBypass()
1574 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal() argument
1579 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1591 Changed |= enableSC0Bit(MI); in enableVolatileAndOrNonTemporal()
1592 Changed |= enableSC1Bit(MI); in enableVolatileAndOrNonTemporal()
1599 Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false, in enableVolatileAndOrNonTemporal()
1606 Changed |= enableNTBit(MI); in enableVolatileAndOrNonTemporal()
1613 bool SIGfx940CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire() argument
1622 MachineBasicBlock &MBB = *MI->getParent(); in insertAcquire()
1623 DebugLoc DL = MI->getDebugLoc(); in insertAcquire()
1626 ++MI; in insertAcquire()
1634 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_INV)) in insertAcquire()
1648 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_INV)) in insertAcquire()
1666 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_INV)) in insertAcquire()
1694 --MI; in insertAcquire()
1699 bool SIGfx940CacheControl::insertRelease(MachineBasicBlock::iterator &MI, in insertRelease() argument
1706 MachineBasicBlock &MBB = *MI->getParent(); in insertRelease()
1707 DebugLoc DL = MI->getDebugLoc(); in insertRelease()
1710 ++MI; in insertRelease()
1721 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_WBL2)) in insertRelease()
1730 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_WBL2)) in insertRelease()
1752 --MI; in insertRelease()
1756 Changed |= insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE, in insertRelease()
1763 const MachineBasicBlock::iterator &MI, in enableLoadCacheBypass() argument
1766 assert(MI->mayLoad() && !MI->mayStore()); in enableLoadCacheBypass()
1775 Changed |= enableGLCBit(MI); in enableLoadCacheBypass()
1776 Changed |= enableDLCBit(MI); in enableLoadCacheBypass()
1784 Changed |= enableGLCBit(MI); in enableLoadCacheBypass()
1806 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal() argument
1812 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1827 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
1828 Changed |= enableDLCBit(MI); in enableVolatileAndOrNonTemporal()
1836 Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false, in enableVolatileAndOrNonTemporal()
1847 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
1848 Changed |= enableSLCBit(MI); in enableVolatileAndOrNonTemporal()
1856 bool SIGfx10CacheControl::insertWait(MachineBasicBlock::iterator &MI, in insertWait() argument
1864 MachineBasicBlock &MBB = *MI->getParent(); in insertWait()
1865 DebugLoc DL = MI->getDebugLoc(); in insertWait()
1868 ++MI; in insertWait()
1959 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate); in insertWait()
1964 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT_VSCNT)) in insertWait()
1971 --MI; in insertWait()
1976 bool SIGfx10CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, in insertAcquire() argument
1985 MachineBasicBlock &MBB = *MI->getParent(); in insertAcquire()
1986 DebugLoc DL = MI->getDebugLoc(); in insertAcquire()
1989 ++MI; in insertAcquire()
1995 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV)); in insertAcquire()
1996 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL1_INV)); in insertAcquire()
2005 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV)); in insertAcquire()
2026 --MI; in insertAcquire()
2032 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope, in enableLoadCacheBypass() argument
2034 assert(MI->mayLoad() && !MI->mayStore()); in enableLoadCacheBypass()
2043 Changed |= enableGLCBit(MI); in enableLoadCacheBypass()
2051 Changed |= enableGLCBit(MI); in enableLoadCacheBypass()
2073 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, in enableVolatileAndOrNonTemporal() argument
2079 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
2094 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
2097 Changed |= enableDLCBit(MI); in enableVolatileAndOrNonTemporal()
2104 Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false, in enableVolatileAndOrNonTemporal()
2115 Changed |= enableGLCBit(MI); in enableVolatileAndOrNonTemporal()
2116 Changed |= enableSLCBit(MI); in enableVolatileAndOrNonTemporal()
2119 Changed |= enableDLCBit(MI); in enableVolatileAndOrNonTemporal()
2130 for (auto &MI : AtomicPseudoMIs) in removeAtomicPseudoMIs() local
2131 MI->eraseFromParent(); in removeAtomicPseudoMIs()
2138 MachineBasicBlock::iterator &MI) { in expandLoad() argument
2139 assert(MI->mayLoad() && !MI->mayStore()); in expandLoad()
2147 Changed |= CC->enableLoadCacheBypass(MI, MOI.getScope(), in expandLoad()
2152 Changed |= CC->insertWait(MI, MOI.getScope(), in expandLoad()
2160 Changed |= CC->insertWait(MI, MOI.getScope(), in expandLoad()
2165 Changed |= CC->insertAcquire(MI, MOI.getScope(), in expandLoad()
2176 Changed |= CC->enableVolatileAndOrNonTemporal(MI, MOI.getInstrAddrSpace(), in expandLoad()
2183 MachineBasicBlock::iterator &MI) { in expandStore() argument
2184 assert(!MI->mayLoad() && MI->mayStore()); in expandStore()
2192 Changed |= CC->enableStoreCacheBypass(MI, MOI.getScope(), in expandStore()
2198 Changed |= CC->insertRelease(MI, MOI.getScope(), in expandStore()
2210 MI, MOI.getInstrAddrSpace(), SIMemOp::STORE, MOI.isVolatile(), in expandStore()
2216 MachineBasicBlock::iterator &MI) { in expandAtomicFence() argument
2217 assert(MI->getOpcode() == AMDGPU::ATOMIC_FENCE); in expandAtomicFence()
2219 AtomicPseudoMIs.push_back(MI); in expandAtomicFence()
2234 Changed |= CC->insertRelease(MI, MOI.getScope(), in expandAtomicFence()
2247 Changed |= CC->insertAcquire(MI, MOI.getScope(), in expandAtomicFence()
2258 MachineBasicBlock::iterator &MI) { in expandAtomicCmpxchgOrRmw() argument
2259 assert(MI->mayLoad() && MI->mayStore()); in expandAtomicCmpxchgOrRmw()
2269 Changed |= CC->enableRMWCacheBypass(MI, MOI.getScope(), in expandAtomicCmpxchgOrRmw()
2277 Changed |= CC->insertRelease(MI, MOI.getScope(), in expandAtomicCmpxchgOrRmw()
2287 Changed |= CC->insertWait(MI, MOI.getScope(), in expandAtomicCmpxchgOrRmw()
2289 isAtomicRet(*MI) ? SIMemOp::LOAD : in expandAtomicCmpxchgOrRmw()
2293 Changed |= CC->insertAcquire(MI, MOI.getScope(), in expandAtomicCmpxchgOrRmw()
2311 for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) { in runOnMachineFunction() local
2314 if (MI->isBundle() && MI->mayLoadOrStore()) { in runOnMachineFunction()
2315 MachineBasicBlock::instr_iterator II(MI->getIterator()); in runOnMachineFunction()
2324 MI->eraseFromParent(); in runOnMachineFunction()
2325 MI = II->getIterator(); in runOnMachineFunction()
2328 if (!(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic)) in runOnMachineFunction()
2331 if (const auto &MOI = MOA.getLoadInfo(MI)) in runOnMachineFunction()
2332 Changed |= expandLoad(MOI.value(), MI); in runOnMachineFunction()
2333 else if (const auto &MOI = MOA.getStoreInfo(MI)) in runOnMachineFunction()
2334 Changed |= expandStore(MOI.value(), MI); in runOnMachineFunction()
2335 else if (const auto &MOI = MOA.getAtomicFenceInfo(MI)) in runOnMachineFunction()
2336 Changed |= expandAtomicFence(MOI.value(), MI); in runOnMachineFunction()
2337 else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI)) in runOnMachineFunction()
2338 Changed |= expandAtomicCmpxchgOrRmw(MOI.value(), MI); in runOnMachineFunction()