49   bool LowerSubregToReg(MachineInstr *MI);
50   bool LowerCopy(MachineInstr *MI);
52   void TransferImplicitOperands(MachineInstr *MI);
65 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {  in TransferImplicitOperands()  argument
66   MachineBasicBlock::iterator CopyMI = MI;  in TransferImplicitOperands()
69   Register DstReg = MI->getOperand(0).getReg();  in TransferImplicitOperands()
70   for (const MachineOperand &MO : MI->implicit_operands()) {  in TransferImplicitOperands()
81 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {  in LowerSubregToReg()  argument
82   MachineBasicBlock *MBB = MI->getParent();  in LowerSubregToReg()
83   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&  in LowerSubregToReg()
84          MI->getOperand(1).isImm() &&  in LowerSubregToReg()
85          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&  in LowerSubregToReg()
86           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");  in LowerSubregToReg()
88   Register DstReg = MI->getOperand(0).getReg();  in LowerSubregToReg()
89   Register InsReg = MI->getOperand(2).getReg();  in LowerSubregToReg()
90   assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");  in LowerSubregToReg()
91   unsigned SubIdx  = MI->getOperand(3).getImm();  in LowerSubregToReg()
101   LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);  in LowerSubregToReg()
103   if (MI->allDefsAreDead()) {  in LowerSubregToReg()
104     MI->setDesc(TII->get(TargetOpcode::KILL));  in LowerSubregToReg()
105     MI->removeOperand(3); // SubIdx  in LowerSubregToReg()
106     MI->removeOperand(1); // Imm  in LowerSubregToReg()
107     LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);  in LowerSubregToReg()
117       MI->setDesc(TII->get(TargetOpcode::KILL));  in LowerSubregToReg()
118       MI->removeOperand(3);     // SubIdx  in LowerSubregToReg()
119       MI->removeOperand(1);     // Imm  in LowerSubregToReg()
120       LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);  in LowerSubregToReg()
125     TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,  in LowerSubregToReg()
126                      MI->getOperand(2).isKill());  in LowerSubregToReg()
129     MachineBasicBlock::iterator CopyMI = MI;  in LowerSubregToReg()
136   MBB->erase(MI);  in LowerSubregToReg()
140 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {  in LowerCopy()  argument
142   if (MI->allDefsAreDead()) {  in LowerCopy()
143     LLVM_DEBUG(dbgs() << "dead copy: " << *MI);  in LowerCopy()
144     MI->setDesc(TII->get(TargetOpcode::KILL));  in LowerCopy()
145     LLVM_DEBUG(dbgs() << "replaced by: " << *MI);  in LowerCopy()
149   MachineOperand &DstMO = MI->getOperand(0);  in LowerCopy()
150   MachineOperand &SrcMO = MI->getOperand(1);  in LowerCopy()
155                       << *MI);  in LowerCopy()
158     if (SrcMO.isUndef() || MI->getNumOperands() > 2) {  in LowerCopy()
161       MI->setDesc(TII->get(TargetOpcode::KILL));  in LowerCopy()
162       LLVM_DEBUG(dbgs() << "replaced by:   " << *MI);  in LowerCopy()
166     MI->eraseFromParent();  in LowerCopy()
170   LLVM_DEBUG(dbgs() << "real copy:   " << *MI);  in LowerCopy()
171   TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),  in LowerCopy()
174   if (MI->getNumOperands() > 2)  in LowerCopy()
175     TransferImplicitOperands(MI);  in LowerCopy()
177     MachineBasicBlock::iterator dMI = MI;  in LowerCopy()
180   MI->eraseFromParent();  in LowerCopy()
197     for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {  in runOnMachineFunction()
199       if (!MI.isPseudo())  in runOnMachineFunction()
203       if (TII->expandPostRAPseudo(MI)) {  in runOnMachineFunction()
209       switch (MI.getOpcode()) {  in runOnMachineFunction()
211         MadeChange |= LowerSubregToReg(&MI);  in runOnMachineFunction()
214         MadeChange |= LowerCopy(&MI);  in runOnMachineFunction()