Lines Matching refs:MI
47 for (MachineInstr &MI : MBB) { in addConstantsToTrack()
48 if (!isSpvIntrinsic(MI, Intrinsic::spv_track_constant)) in addConstantsToTrack()
50 ToErase.push_back(&MI); in addConstantsToTrack()
53 MI.getOperand(3).getMetadata()->getOperand(0)) in addConstantsToTrack()
58 GR->add(GV, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
60 RegsAlreadyAddedToDT[&MI] = Reg; in addConstantsToTrack()
65 auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
72 GR->add(Const, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
74 RegsAlreadyAddedToDT[&MI] = Reg; in addConstantsToTrack()
77 assert(MI.getOperand(2).isReg() && "Reg operand is expected"); in addConstantsToTrack()
78 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
85 for (MachineInstr *MI : ToErase) { in addConstantsToTrack()
86 Register Reg = MI->getOperand(2).getReg(); in addConstantsToTrack()
87 if (RegsAlreadyAddedToDT.find(MI) != RegsAlreadyAddedToDT.end()) in addConstantsToTrack()
88 Reg = RegsAlreadyAddedToDT[MI]; in addConstantsToTrack()
89 MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg); in addConstantsToTrack()
90 MI->eraseFromParent(); in addConstantsToTrack()
92 for (MachineInstr *MI : ToEraseComposites) in addConstantsToTrack()
93 MI->eraseFromParent(); in addConstantsToTrack()
101 for (MachineInstr &MI : MBB) { in foldConstantsIntoIntrinsics()
102 if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_name)) in foldConstantsIntoIntrinsics()
104 unsigned NumOp = MI.getNumExplicitDefs() + AssignNameOperandShift; in foldConstantsIntoIntrinsics()
105 while (MI.getOperand(NumOp).isReg()) { in foldConstantsIntoIntrinsics()
106 MachineOperand &MOp = MI.getOperand(NumOp); in foldConstantsIntoIntrinsics()
109 MI.removeOperand(NumOp); in foldConstantsIntoIntrinsics()
110 MI.addOperand(MachineOperand::CreateImm( in foldConstantsIntoIntrinsics()
117 for (MachineInstr *MI : ToErase) in foldConstantsIntoIntrinsics()
118 MI->eraseFromParent(); in foldConstantsIntoIntrinsics()
125 for (MachineInstr &MI : MBB) { in insertBitcasts()
126 if (!isSpvIntrinsic(MI, Intrinsic::spv_bitcast)) in insertBitcasts()
128 assert(MI.getOperand(2).isReg()); in insertBitcasts()
129 MIB.setInsertPt(*MI.getParent(), MI); in insertBitcasts()
130 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
131 ToErase.push_back(&MI); in insertBitcasts()
134 for (MachineInstr *MI : ToErase) in insertBitcasts()
135 MI->eraseFromParent(); in insertBitcasts()
146 static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR, in propagateSPIRVType() argument
150 assert(MI && "Machine instr is expected"); in propagateSPIRVType()
151 if (MI->getOperand(0).isReg()) { in propagateSPIRVType()
152 Register Reg = MI->getOperand(0).getReg(); in propagateSPIRVType()
155 switch (MI->getOpcode()) { in propagateSPIRVType()
157 MIB.setInsertPt(*MI->getParent(), MI); in propagateSPIRVType()
158 Type *Ty = MI->getOperand(1).getCImm()->getType(); in propagateSPIRVType()
163 MIB.setInsertPt(*MI->getParent(), MI); in propagateSPIRVType()
164 Type *Ty = MI->getOperand(1).getGlobal()->getType(); in propagateSPIRVType()
172 MachineOperand &Op = MI->getOperand(1); in propagateSPIRVType()
232 MachineInstr &MI = *MII; in generateAssignInstrs() local
234 if (isSpvIntrinsic(MI, Intrinsic::spv_assign_type)) { in generateAssignInstrs()
235 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
236 Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0); in generateAssignInstrs()
242 ToErase.push_back(&MI); in generateAssignInstrs()
243 } else if (MI.getOpcode() == TargetOpcode::G_CONSTANT || in generateAssignInstrs()
244 MI.getOpcode() == TargetOpcode::G_FCONSTANT || in generateAssignInstrs()
245 MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR) { in generateAssignInstrs()
251 Register Reg = MI.getOperand(0).getReg(); in generateAssignInstrs()
259 if (MI.getOpcode() == TargetOpcode::G_CONSTANT) in generateAssignInstrs()
260 Ty = MI.getOperand(1).getCImm()->getType(); in generateAssignInstrs()
261 else if (MI.getOpcode() == TargetOpcode::G_FCONSTANT) in generateAssignInstrs()
262 Ty = MI.getOperand(1).getFPImm()->getType(); in generateAssignInstrs()
264 assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR); in generateAssignInstrs()
266 MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in generateAssignInstrs()
276 MI.getNumExplicitOperands() - MI.getNumExplicitDefs(); in generateAssignInstrs()
280 } else if (MI.getOpcode() == TargetOpcode::G_TRUNC || in generateAssignInstrs()
281 MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE || in generateAssignInstrs()
282 MI.getOpcode() == TargetOpcode::COPY || in generateAssignInstrs()
283 MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) { in generateAssignInstrs()
284 propagateSPIRVType(&MI, GR, MRI, MIB); in generateAssignInstrs()
293 for (MachineInstr *MI : ToErase) in generateAssignInstrs()
294 MI->eraseFromParent(); in generateAssignInstrs()
325 static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, in processInstr() argument
327 unsigned Opc = MI.getOpcode(); in processInstr()
328 assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg())); in processInstr()
330 *(MRI.use_instr_begin(MI.getOperand(0).getReg())); in processInstr()
331 auto NewReg = createNewIdReg(MI.getOperand(0).getReg(), Opc, MRI, *GR).first; in processInstr()
333 MI.getOperand(0).setReg(NewReg); in processInstr()
334 MIB.setInsertPt(*MI.getParent(), in processInstr()
335 (MI.getNextNode() ? MI.getNextNode()->getIterator() in processInstr()
336 : MI.getParent()->end())); in processInstr()
337 for (auto &Op : MI.operands()) { in processInstr()
354 for (MachineInstr &MI : MBB) { in processInstrsWithTypeFolding()
355 if (isTypeFoldingSupported(MI.getOpcode())) in processInstrsWithTypeFolding()
356 processInstr(MI, MIB, MRI, GR); in processInstrsWithTypeFolding()
360 for (MachineInstr &MI : MBB) { in processInstrsWithTypeFolding()
364 if (MI.getOpcode() != SPIRV::ASSIGN_TYPE) in processInstrsWithTypeFolding()
366 Register SrcReg = MI.getOperand(1).getReg(); in processInstrsWithTypeFolding()
369 Register DstReg = MI.getOperand(0).getReg(); in processInstrsWithTypeFolding()
404 for (MachineInstr &MI : MBB) { in processSwitches()
405 if (isSpvIntrinsic(MI, Intrinsic::spv_switch)) { in processSwitches()
406 assert(MI.getOperand(1).isReg()); in processSwitches()
407 Register Reg = MI.getOperand(1).getReg(); in processSwitches()
413 if (MI.getOpcode() == TargetOpcode::G_ICMP && MI.getOperand(2).isReg() && in processSwitches()
414 SwitchRegs.contains(MI.getOperand(2).getReg())) { in processSwitches()
415 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isPredicate() && in processSwitches()
416 MI.getOperand(3).isReg()); in processSwitches()
417 Register Dst = MI.getOperand(0).getReg(); in processSwitches()
420 MIB.setInsertPt(*MI.getParent(), MI); in processSwitches()
426 Register CmpReg = MI.getOperand(2).getReg(); in processSwitches()
427 MachineOperand &PredOp = MI.getOperand(1); in processSwitches()
431 uint64_t Val = getIConstVal(MI.getOperand(3).getReg(), &MRI); in processSwitches()
456 for (MachineInstr &MI : MBB) { in processSwitches()
457 if (!isSpvIntrinsic(MI, Intrinsic::spv_switch)) in processSwitches()
459 assert(MI.getOperand(1).isReg()); in processSwitches()
460 Register Reg = MI.getOperand(1).getReg(); in processSwitches()
461 unsigned NumOp = MI.getNumExplicitOperands(); in processSwitches()
465 Register CReg = MI.getOperand(i).getReg(); in processSwitches()
471 for (unsigned i = MI.getNumExplicitOperands() - 1; i > 1; i--) in processSwitches()
472 MI.removeOperand(i); in processSwitches()
473 MI.addOperand(MachineOperand::CreateMBB(DefaultMBBs[Reg])); in processSwitches()
475 MI.addOperand(MachineOperand::CreateCImm(Vals[i])); in processSwitches()
476 MI.addOperand(MachineOperand::CreateMBB(MBBs[i])); in processSwitches()