42 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,  in getDirectBrEncoding()  argument
45   const MCOperand &MO = MI.getOperand(OpNo);  in getDirectBrEncoding()
48     return getMachineOpValue(MI, MO, Fixups, STI);  in getDirectBrEncoding()
51   unsigned Opcode = MI.getOpcode();  in getDirectBrEncoding()
60 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,  in getCondBrEncoding()  argument
63   const MCOperand &MO = MI.getOperand(OpNo);  in getCondBrEncoding()
64   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getCondBrEncoding()
73 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,  in getAbsDirectBrEncoding()  argument
76   const MCOperand &MO = MI.getOperand(OpNo);  in getAbsDirectBrEncoding()
77   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getAbsDirectBrEncoding()
86 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,  in getAbsCondBrEncoding()  argument
89   const MCOperand &MO = MI.getOperand(OpNo);  in getAbsCondBrEncoding()
90   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getAbsCondBrEncoding()
99 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,  in getVSRpEvenEncoding()  argument
102   assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");  in getVSRpEvenEncoding()
103   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)  in getVSRpEvenEncoding()
108 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,  in getImm16Encoding()  argument
111   const MCOperand &MO = MI.getOperand(OpNo);  in getImm16Encoding()
112   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getImm16Encoding()
120 uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,  in getImm34Encoding()  argument
124   const MCOperand &MO = MI.getOperand(OpNo);  in getImm34Encoding()
127     return getMachineOpValue(MI, MO, Fixups, STI);  in getImm34Encoding()
135 PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,  in getImm34EncodingNoPCRel()  argument
138   return getImm34Encoding(MI, OpNo, Fixups, STI,  in getImm34EncodingNoPCRel()
143 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,  in getImm34EncodingPCRel()  argument
146   return getImm34Encoding(MI, OpNo, Fixups, STI,  in getImm34EncodingPCRel()
150 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,  in getMemRIEncoding()  argument
155   assert(MI.getOperand(OpNo+1).isReg());  in getMemRIEncoding()
156   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;  in getMemRIEncoding()
158   const MCOperand &MO = MI.getOperand(OpNo);  in getMemRIEncoding()
160     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;  in getMemRIEncoding()
168 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,  in getMemRIXEncoding()  argument
173   assert(MI.getOperand(OpNo+1).isReg());  in getMemRIXEncoding()
174   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;  in getMemRIXEncoding()
176   const MCOperand &MO = MI.getOperand(OpNo);  in getMemRIXEncoding()
178     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;  in getMemRIXEncoding()
186 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,  in getMemRIX16Encoding()  argument
191   assert(MI.getOperand(OpNo+1).isReg());  in getMemRIX16Encoding()
192   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;  in getMemRIX16Encoding()
194   const MCOperand &MO = MI.getOperand(OpNo);  in getMemRIX16Encoding()
198     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;  in getMemRIX16Encoding()
208 PPCMCCodeEmitter::getMemRIHashEncoding(const MCInst &MI, unsigned OpNo,  in getMemRIHashEncoding()  argument
213   const MCOperand &RegMO = MI.getOperand(OpNo + 1);  in getMemRIHashEncoding()
214   const MCOperand &MO = MI.getOperand(OpNo);  in getMemRIHashEncoding()
220   unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6;  in getMemRIHashEncoding()
226 PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,  in getMemRI34PCRelEncoding()  argument
239   assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");  in getMemRI34PCRelEncoding()
241     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;  in getMemRI34PCRelEncoding()
246   const MCOperand &MO = MI.getOperand(OpNo);  in getMemRI34PCRelEncoding()
248     return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;  in getMemRI34PCRelEncoding()
316 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,  in getMemRI34Encoding()  argument
321   assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");  in getMemRI34Encoding()
322   uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)  in getMemRI34Encoding()
324   const MCOperand &MO = MI.getOperand(OpNo);  in getMemRI34Encoding()
325   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;  in getMemRI34Encoding()
328 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,  in getSPE8DisEncoding()  argument
334   assert(MI.getOperand(OpNo+1).isReg());  in getSPE8DisEncoding()
335   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;  in getSPE8DisEncoding()
337   const MCOperand &MO = MI.getOperand(OpNo);  in getSPE8DisEncoding()
339   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;  in getSPE8DisEncoding()
343 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,  in getSPE4DisEncoding()  argument
349   assert(MI.getOperand(OpNo+1).isReg());  in getSPE4DisEncoding()
350   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;  in getSPE4DisEncoding()
352   const MCOperand &MO = MI.getOperand(OpNo);  in getSPE4DisEncoding()
354   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;  in getSPE4DisEncoding()
358 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,  in getSPE2DisEncoding()  argument
364   assert(MI.getOperand(OpNo+1).isReg());  in getSPE2DisEncoding()
365   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;  in getSPE2DisEncoding()
367   const MCOperand &MO = MI.getOperand(OpNo);  in getSPE2DisEncoding()
369   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;  in getSPE2DisEncoding()
373 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,  in getTLSRegEncoding()  argument
376   const MCOperand &MO = MI.getOperand(OpNo);  in getTLSRegEncoding()
377   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);  in getTLSRegEncoding()
393 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,  in getTLSCallEncoding()  argument
399   const MCOperand &MO = MI.getOperand(OpNo+1);  in getTLSCallEncoding()
402   return getDirectBrEncoding(MI, OpNo, Fixups, STI);  in getTLSCallEncoding()
406 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,  in get_crbitm_encoding()  argument
409   const MCOperand &MO = MI.getOperand(OpNo);  in get_crbitm_encoding()
410   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||  in get_crbitm_encoding()
411           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&  in get_crbitm_encoding()
420 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {  in getOpIdxForMO()  argument
421   for (unsigned i = 0; i < MI.getNumOperands(); i++) {  in getOpIdxForMO()
422     const MCOperand &Op = MI.getOperand(i);  in getOpIdxForMO()
431 getMachineOpValue(const MCInst &MI, const MCOperand &MO,  in getMachineOpValue()  argument
437     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&  in getMachineOpValue()
438             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||  in getMachineOpValue()
440     unsigned OpNo = getOpIdxForMO(MI, MO);  in getMachineOpValue()
442       PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),  in getMachineOpValue()
452 void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,  in encodeInstruction()  argument
455   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);  in encodeInstruction()
458   unsigned Size = getInstSizeInBytes(MI);  in encodeInstruction()
480 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {  in getInstSizeInBytes()
481   unsigned Opcode = MI.getOpcode();  in getInstSizeInBytes()
486 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {  in isPrefixedInstruction()
487   unsigned Opcode = MI.getOpcode();  in isPrefixedInstruction()