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Searched refs:Lane (Results 1 – 25 of 42) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
88 unsigned Lane, unsigned ToInsert);
416 unsigned Lane, bool QPR) { in createDupLane() argument
422 .addImm(Lane) in createDupLane()
431 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
438 .addReg(DReg, 0, Lane); in createExtractSubreg()
484 .addImm(Lane); in createInsertSubreg()
541 unsigned Lane; in optimizeAllLanesPattern() local
543 case ARM::ssub_0: Lane = 0; break; in optimizeAllLanesPattern()
544 case ARM::ssub_1: Lane = 1; break; in optimizeAllLanesPattern()
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H A DARMBaseInstrInfo.cpp5054 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
5056 Lane = 0; in getCorrespondingDRegAndLane()
5061 Lane = 1; in getCorrespondingDRegAndLane()
5085 unsigned Lane, unsigned &ImplicitSReg) { in getImplicitSPRUseForDPRUse() argument
5095 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
5113 unsigned Lane; in setExecutionDomain() local
5156 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); in setExecutionDomain()
5164 .addImm(Lane) in setExecutionDomain()
5180 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); in setExecutionDomain()
5183 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) in setExecutionDomain()
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/llvm-project-15.0.7/openmp/libomptarget/DeviceRTL/src/
H A DMapping.cpp73 uint32_t Lane = mapping::getThreadIdInWarp(); in lanemaskLT() local
75 uint64_t Mask = ((uint64_t)1 << Lane) - (uint64_t)1; in lanemaskLT()
80 uint32_t Lane = mapping::getThreadIdInWarp(); in lanemaskGT() local
81 if (Lane == (mapping::getWarpSize() - 1)) in lanemaskGT()
84 uint64_t Mask = (~((uint64_t)0)) << (Lane + 1); in lanemaskGT()
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DVPlanSLP.cpp312 for (unsigned Lane = 1, E = MultiNodeOps[0].second.size(); Lane < E; ++Lane) { in reorderMultiNodeOps() local
313 LLVM_DEBUG(dbgs() << " Finding best value for lane " << Lane << "\n"); in reorderMultiNodeOps()
318 dbgs() << *cast<VPInstruction>(Ops.second[Lane])->getUnderlyingInstr() in reorderMultiNodeOps()
320 Candidates.insert(Ops.second[Lane]); in reorderMultiNodeOps()
329 VPValue *Last = FinalOrder[Op].second[Lane - 1]; in reorderMultiNodeOps()
H A DVPlan.cpp68 Builder.getInt32(VF.getKnownMinValue() - Lane)); in getAsRuntimeExpr()
70 return Builder.getInt32(Lane); in getAsRuntimeExpr()
210 .PerPartScalars[Def][Instance.Part][Instance.Lane.mapToCacheIndex(VF)]; in get()
216 assert(Instance.Lane.isFirstLane() && "cannot get lane > 0 for scalar"); in get()
220 Value *Lane = Instance.Lane.getAsRuntimeExpr(Builder, VF); in get() local
221 auto *Extract = Builder.CreateExtractElement(VecPart, Lane); in get()
541 for (unsigned Lane = 0, VF = State->VF.getKnownMinValue(); Lane < VF; in execute() local
542 ++Lane) { in execute()
543 State->Instance->Lane = VPLane(Lane, VPLane::Kind::First); in execute()
H A DVPlan.h124 unsigned Lane;
130 VPLane(unsigned Lane, Kind LaneKind) : Lane(Lane), LaneKind(LaneKind) {} in VPLane() argument
150 return Lane; in getKnownLane()
168 return VF.getKnownMinValue() + Lane; in mapToCacheIndex()
170 assert(Lane < VF.getKnownMinValue()); in mapToCacheIndex()
171 return Lane; in mapToCacheIndex()
188 VPLane Lane; member
190 VPIteration(unsigned Part, unsigned Lane,
192 : Part(Part), Lane(Lane, Kind) {} in Part()
194 VPIteration(unsigned Part, const VPLane &Lane) : Part(Part), Lane(Lane) {} in VPIteration()
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H A DSLPVectorizer.cpp1403 ++Lane) in clearUsed()
1409 std::swap(OpsVec[OpIdx1][Lane], OpsVec[OpIdx2][Lane]); in swap()
1744 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in appendOperandsOfVL() local
1822 for (unsigned Lane = 0, Lanes = getNumLanes(); Lane != Lanes; ++Lane) in getVL() local
1823 OpVL[Lane] = OpsVec[OpIdx][Lane].V; in getVL()
1925 if (Lane < 0 || Lane >= (int)NumLanes) in reorder()
2345 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in setOperandsInOrder() local
2626 int Lane; member
4235 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { in buildExternalUses() local
8493 Value *Lane = Builder.getInt32(ExternalUse.Lane); in vectorizeTree() local
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H A DVPlanRecipes.cpp133 auto Lane = VPLane::getLastLaneForVF(State.VF); in fixPhi() local
136 Lane = VPLane::getFirstLane(); in fixPhi()
137 Phi->addIncoming(State.get(ExitValue, VPIteration(State.UF - 1, Lane)), in fixPhi()
873 unsigned Lane = State.Instance->Lane.getKnownLane(); in execute() local
881 ConditionBit, State.Builder.getInt32(Lane)); in execute()
H A DLoopVectorize.cpp2379 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in buildScalarSteps() local
2389 State.set(Def, Add, VPIteration(Part, Lane)); in buildScalarSteps()
2498 Instance.Lane.getAsRuntimeExpr(State.Builder, VF)); in packScalarIntoVectorValue()
2780 InputInstance.Lane = VPLane::getFirstLane(); in scalarizeInstruction()
9357 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in execute() local
9359 PartStart, ConstantInt::get(PtrInd->getType(), Lane)); in execute()
9367 State.set(this, SclrGep, VPIteration(Part, Lane)); in execute()
9552 if (State.Instance->Lane.isFirstLane()) { in execute()
9577 for (unsigned Lane = 0; Lane < EndLane; ++Lane) in execute() local
9819 for (unsigned Lane = 0; Lane < VF.getKnownMinValue(); ++Lane) in get() local
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2102 return Lane->getOperand(0); in LowerBUILD_VECTOR()
2136 if (Lane.isUndef()) in LowerBUILD_VECTOR()
2139 AddCount(SplatValueCounts, Lane); in LowerBUILD_VECTOR()
2141 if (IsConstant(Lane)) in LowerBUILD_VECTOR()
2219 SDValue Src = GetShuffleSrc(Lane); in LowerBUILD_VECTOR()
2231 auto Src = GetShuffleSrc(Lane); in LowerBUILD_VECTOR()
2237 if (IsConstant(Lane)) { in LowerBUILD_VECTOR()
2253 ConstLanes.push_back(Lane); in LowerBUILD_VECTOR()
2263 return IsConstant(Lane); in LowerBUILD_VECTOR()
2279 return Lane == SplatValue; in LowerBUILD_VECTOR()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp301 static bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI, in matchDupFromInsertVectorElt() argument
304 if (Lane != 0) in matchDupFromInsertVectorElt()
340 static bool matchDupFromBuildVector(int Lane, MachineInstr &MI, in matchDupFromBuildVector() argument
343 assert(Lane >= 0 && "Expected positive lane?"); in matchDupFromBuildVector()
350 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg(); in matchDupFromBuildVector()
362 int Lane = *MaybeLane; in matchDup() local
364 if (Lane < 0) in matchDup()
365 Lane = 0; in matchDup()
366 if (matchDupFromInsertVectorElt(Lane, MI, MRI, MatchInfo)) in matchDup()
368 if (matchDupFromBuildVector(Lane, MI, MRI, MatchInfo)) in matchDup()
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/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DLaneBitmask.h85 static constexpr LaneBitmask getLane(unsigned Lane) { in getLane()
86 return LaneBitmask(Type(1) << Lane); in getLane()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp445 for (int Lane = 0; Lane < LaneCount; Lane++) in createShuffleStride() local
447 Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane); in createShuffleStride()
617 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle() local
619 IndexGroup[(Index * 3) % (VF / Lane)] = Index; in group2Shuffle()
623 for (int i = 0; i < VF / Lane; i++) { in group2Shuffle()
H A DX86InstCombineIntrinsic.cpp491 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack() local
493 PackMask.push_back(Elt + (Lane * NumSrcEltsPerLane)); in simplifyX86pack()
495 PackMask.push_back(Elt + (Lane * NumSrcEltsPerLane) + NumSrcElts); in simplifyX86pack()
1976 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic() local
1977 unsigned LaneIdx = Lane * VWidthPerLane; in simplifyDemandedVectorEltsIntrinsic()
1981 OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt); in simplifyDemandedVectorEltsIntrinsic()
1991 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic() local
1992 APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane); in simplifyDemandedVectorEltsIntrinsic()
1994 LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum); in simplifyDemandedVectorEltsIntrinsic()
H A DX86ISelLowering.cpp7554 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in createPackShuffleMask() local
7577 for (int Lane = 0; Lane != NumLanes; ++Lane) { in getPackDemandedElts() local
13019 for (int Lane = 0; Lane != NumElts; Lane += NumLaneElts) { in lowerShuffleAsUNPCKAndPermute() local
13048 for (int Lane = 0; Lane != NumElts; Lane += NumLaneElts) { in lowerShuffleAsUNPCKAndPermute() local
13091 for (int Lane = 0; Lane != NumElts; Lane += NumEltsPerLane) { in lowerShuffleAsByteRotateAndPermute() local
13131 for (int Lane = 0; Lane != NumElts; Lane += NumEltsPerLane) { in lowerShuffleAsByteRotateAndPermute() local
17070 for (int Lane = 0; Lane != NumLanes; ++Lane) { in lowerShuffleAsLanePermuteAndRepeatedMask() local
17142 for (int Lane = 0; Lane != NumLanes; ++Lane) { in lowerShuffleAsLanePermuteAndRepeatedMask() local
17172 for (int Lane = 0; Lane != NumLanes; ++Lane) { in lowerShuffleAsLanePermuteAndRepeatedMask() local
17189 for (int Lane = 0; Lane != NumLanes; ++Lane) { in lowerShuffleAsLanePermuteAndRepeatedMask() local
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h56 int Lane = -1; member
59 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} in SpilledReg()
61 bool hasLane() { return Lane != -1; } in hasLane()
H A DSIRegisterInfo.cpp1154 int Index, unsigned Lane, in spillVGPRtoAGPR() argument
1160 MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane); in spillVGPRtoAGPR()
1512 for (int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS, in buildSpillLoadStore() local
1514 Lane >= LaneE; --Lane) { in buildSpillLoadStore()
1517 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1519 auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill); in buildSpillLoadStore()
1522 if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == LaneS && !i)) { in buildSpillLoadStore()
1529 if (Lane != LaneE) in buildSpillLoadStore()
1703 .addImm(Spill.Lane) in spillSGPR()
1811 .addImm(Spill.Lane); in restoreSGPR()
H A DSIMachineFunctionInfo.h573 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
576 : I->second.Lanes[Lane];
H A DSIFrameLowering.cpp85 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
106 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';); in getVGPRSpillLaneOrTempRegister()
837 .addImm(Spill[0].Lane) in emitPrologue()
1025 .addImm(Spill[0].Lane); in emitEpilogue()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DInterleavedAccessPass.cpp231 unsigned Lane = J * Factor + I; in isReInterleaveMask() local
232 unsigned NextLane = Lane + Factor; in isReInterleaveMask()
233 int LaneValue = Mask[Lane]; in isReInterleaveMask()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.writelane.ll128 ; Lane is inline imm
149 ; Lane index is larger than the wavesize
171 ; Lane index is larger than the wavesize for wave32
/llvm-project-15.0.7/polly/lib/CodeGen/
H A DBlockGenerators.cpp1030 for (int Lane = 0; Lane < Width; Lane++) in getVectorValue() local
1032 Vector, getNewValue(Stmt, Old, ScalarMaps[Lane], VLTS[Lane], L), in getVectorValue()
1033 Builder.getInt32(Lane)); in getVectorValue()
/llvm-project-15.0.7/llvm/docs/
H A DBigEndianNEON.rst90 LLVM IR Lane ordering
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3167 unsigned Lane = MI.getOperand(2).getImm(); in emitCOPY_FW() local
3169 if (Lane == 0) { in emitCOPY_FW()
3185 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane); in emitCOPY_FW()
3212 unsigned Lane = MI.getOperand(2).getImm() * 2; in emitCOPY_FD() local
3215 if (Lane == 0) in emitCOPY_FD()
3242 unsigned Lane = MI.getOperand(2).getImm(); in emitINSERT_FW() local
3254 .addImm(Lane) in emitINSERT_FW()
3278 unsigned Lane = MI.getOperand(2).getImm(); in emitINSERT_FD() local
3288 .addImm(Lane) in emitINSERT_FD()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10355 Lane += V.getConstantOperandVal(1); in constructDup()
10474 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
10476 if (Lane == -1) in LowerVECTOR_SHUFFLE()
10477 Lane = 0; in LowerVECTOR_SHUFFLE()
10495 unsigned Lane = 0; in LowerVECTOR_SHUFFLE() local
11079 for (SDValue Lane : Op->ops()) { in NormalizeBuildVector() local
11089 Lane = DAG.getUNDEF(MVT::i32); in NormalizeBuildVector()
11094 Ops.push_back(Lane); in NormalizeBuildVector()
15434 SDValue Lane = Op1.getOperand(1); in tryCombineFixedPointConvert() local
17442 SDValue Lane; in performPostLD1Combine() local
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