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/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp81 InstRef IR = HWS.select(); in issueReadyInstructions() local
82 while (IR) { in issueReadyInstructions()
87 IR = HWS.select(); in issueReadyInstructions()
106 for (InstRef &IR : Executed) { in cycleStart()
117 notifyInstructionReady(IR); in cycleStart()
177 notifyInstructionPending(IR); in handleInstructionEliminated()
178 notifyInstructionReady(IR); in handleInstructionEliminated()
191 HWS.instructionCheck(IR); in execute()
213 notifyInstructionPending(IR); in execute()
216 notifyInstructionReady(IR); in execute()
[all …]
H A DInOrderIssueStage.cpp25 IR.invalidate(); in clear()
31 IR = Inst; in update()
124 if (hasResourceHazard(RM, IR)) { in canExecute()
129 if (IR.getInstruction()->isMemOp() && !LSU.isReady(IR)) { in canExecute()
217 if (!canExecute(IR)) { in tryIssue()
238 LSU.onInstructionIssued(IR); in tryIssue()
250 CarriedOver = IR; in tryIssue()
268 retireInstruction(IR); in tryIssue()
272 IssuedInst.push_back(IR); in tryIssue()
286 InstRef &IR = *I; in updateIssuedInst() local
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H A DDispatchStage.cpp72 bool CanDispatch = checkRCU(IR); in canDispatch()
73 CanDispatch &= checkPRF(IR); in canDispatch()
74 CanDispatch &= checkNextStage(IR); in canDispatch()
78 Error DispatchStage::dispatch(InstRef IR) { in dispatch() argument
80 Instruction &IS = *IR.getInstruction(); in dispatch()
86 CarriedOver = IR; in dispatch()
123 unsigned RCUTokenID = RCU.dispatch(IR); in dispatch()
131 return moveToTheNextStage(IR); in dispatch()
171 return canDispatch(IR); in isAvailable()
174 Error DispatchStage::execute(InstRef &IR) { in execute() argument
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/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp71 InstRef &IR, in issueInstructionImpl() argument
100 InstRef &IR, in issueInstruction() argument
124 InstRef &IR = *I; in promoteToReadySet() local
125 if (!IR) in promoteToReadySet()
146 IR.invalidate(); in promoteToReadySet()
160 InstRef &IR = *I; in promoteToPendingSet() local
161 if (!IR) in promoteToPendingSet()
183 IR.invalidate(); in promoteToPendingSet()
215 return IR; in select()
222 if (!IR) in updateIssuedSet()
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsrem64.ll194 ; GCN-IR-NEXT: .LBB0_5:
214 ; GCN-IR-NEXT: s_endpgm
486 ; GCN-IR: ; %bb.0:
557 ; GCN-IR: ; %bb.0:
620 ; GCN-IR: ; %bb.0:
682 ; GCN-IR: ; %bb.0:
753 ; GCN-IR: ; %bb.0:
822 ; GCN-IR: ; %bb.0:
1075 ; GCN-IR-NEXT: .LBB8_5:
1233 ; GCN-IR-NEXT: .LBB9_5:
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H A Dsdiv64.ll222 ; GCN-IR-NEXT: .LBB0_5:
237 ; GCN-IR-NEXT: s_endpgm
504 ; GCN-IR: ; %bb.0:
559 ; GCN-IR: ; %bb.0:
610 ; GCN-IR: ; %bb.0:
674 ; GCN-IR: ; %bb.0:
741 ; GCN-IR: ; %bb.0:
808 ; GCN-IR: ; %bb.0:
891 ; GCN-IR: ; %bb.0:
1066 ; GCN-IR-NEXT: .LBB9_5:
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H A Dudiv64.ll195 ; GCN-IR-NEXT: .LBB0_5:
204 ; GCN-IR-NEXT: s_endpgm
435 ; GCN-IR: ; %bb.0:
485 ; GCN-IR: ; %bb.0:
531 ; GCN-IR: ; %bb.0:
585 ; GCN-IR: ; %bb.0:
642 ; GCN-IR: ; %bb.0:
870 ; GCN-IR-NEXT: .LBB7_5:
1056 ; GCN-IR-NEXT: .LBB8_5:
1715 ; GCN-IR: ; %bb.0:
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H A Durem64.ll194 ; GCN-IR-NEXT: .LBB0_5:
214 ; GCN-IR-NEXT: s_endpgm
450 ; GCN-IR: ; %bb.0:
522 ; GCN-IR: ; %bb.0:
594 ; GCN-IR: ; %bb.0:
666 ; GCN-IR: ; %bb.0:
878 ; GCN-IR-NEXT: .LBB6_5:
1063 ; GCN-IR-NEXT: .LBB7_5:
1388 ; GCN-IR: ; %bb.0:
1442 ; GCN-IR: ; %bb.0:
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H A Dnested-loop-conditions.ll50 ; IR-NEXT: bb:
55 ; IR: bb3:
57 ; IR: bb4:
59 ; IR: bb5:
67 ; IR: bb8:
69 ; IR: bb9:
71 ; IR: bb10:
74 ; IR: Flow:
80 ; IR: bb13:
84 ; IR: bb16:
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H A Dmulti-divergent-exit-region.ll18 ; IR: Flow:
32 ; IR: Flow2:
40 ; IR: exit0:
44 ; IR: Flow1:
53 ; IR: exit1:
59 ; IR: ret void
200 ; IR: br i1
216 ; IR: Flow2:
222 ; IR: exit0:
282 ; IR: Flow:
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H A Dprivate-memory-atomics.ll8 ; IR-NEXT: ret i32 [[LOAD]]
23 ; IR-NEXT: ret i64 [[LOAD]]
40 ; IR-NEXT: ret void
55 ; IR-NEXT: ret void
72 ; IR-NEXT: ret i32 [[LOAD]]
87 ; IR-NEXT: ret void
180 ; IR-NEXT: ret i32 [[TMP1]]
456 ; IR-NEXT: entry:
467 ; IR-NEXT: ret void
495 ; IR-NEXT: entry:
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H A Damdgpu-codegenprepare-fold-binop-select.ll8 ; IR-NEXT: ret i32 [[OP]]
27 ; IR-NEXT: ret i32 [[OP]]
255 ; IR-NEXT: ret i32 [[OP]]
285 ; IR-NEXT: ret i32 [[OP]]
314 ; IR-NEXT: ret i32 [[OP]]
362 ; IR-NEXT: ret i32 [[OP]]
381 ; IR-NEXT: ret i32 [[OP]]
391 ; IR-NEXT: ret void
420 ; IR-NEXT: ret i16 [[OP]]
430 ; IR-NEXT: ret i32 [[OP]]
[all …]
H A Dupdate-phi.ll8 ; IR-LABEL: @_amdgpu_ps_main(
9 ; IR-NEXT: .entry:
10 ; IR-NEXT: br label [[DOTLOOPEXIT:%.*]]
11 ; IR: .loopexit:
12 ; IR-NEXT: br label [[N28:%.*]]
13 ; IR: n28:
18 ; IR: TransitionBlock:
20 ; IR: n31:
21 ; IR-NEXT: ret void
22 ; IR: DummyReturnBlock:
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/llvm-project-15.0.7/polly/test/CodeGen/OpenMP/
H A Dsingle_loop.ll35 ; IR-LABEL: single_parallel_loop()
36 ; IR-NEXT: entry
39 ; IR-LABEL: polly.parallel.for:
47 ; IR-LABEL: polly.par.setup:
53 ; IR-LABEL: polly.par.exit:
55 ; IR-NEXT: ret void
57 ; IR-LABEL: polly.par.checkNext:
68 ; IR-LABEL: polly.loop_exit:
71 ; IR-LABEL: polly.loop_header:
75 ; IR-LABEL: polly.stmt.S:
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/llvm-project-15.0.7/polly/test/GPGPU/
H A Dhost-control-flow.ll8 ; RUN: -S < %s | FileCheck %s -check-prefix=IR
37 ; IR: call i8* @polly_getKernel
39 ; IR: call void @polly_freeKernel
45 ; KERNEL-IR-LABEL: entry:
47 ; KERNEL-IR-NEXT: %b0 = zext i32 %0 to i64
49 ; KERNEL-IR-NEXT: %t0 = zext i32 %1 to i64
50 ; KERNEL-IR-NEXT: br label %polly.cond
59 ; KERNEL-IR-NEXT: ret void
116 ; KERNEL-IR-NEXT: br label %polly.merge
119 ; KERNEL-IR-NEXT: br label %polly.merge
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H A Ddouble-parallel-loop.ll11 ; RUN: FileCheck %s -check-prefix=IR
15 ; RUN: FileCheck %s -check-prefix=KERNEL-IR
91 ; IR: polly.split_new_and_old:
109 ; IR-NEXT: %5 = and i1 true, %4
114 ; IR: polly.start:
117 ; IR: polly.acc.initialize:
127 ; IR-NEXT: call i8* @polly_getKernel
134 ; IR-NEXT: br label %polly.exiting
136 ; IR: polly.exiting:
140 ; KERNEL-IR-NEXT: entry:
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Datomic_optimizations_mul_one.ll13 ; IR-NEXT: .entry:
24 ; IR: 9:
27 ; IR: 11:
63 ; IR: 9:
66 ; IR: 11:
118 ; IR: 9:
121 ; IR: 11:
157 ; IR: 9:
160 ; IR: 11:
213 ; IR: 10:
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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvector-promotion.ll10 ; IR-BOTH-NEXT: ret
31 ; IR-BOTH-NEXT: ret
53 ; IR-BOTH: ret
83 ; IR-BOTH-NEXT: ret
134 ; IR-BOTH-NEXT: ret
153 ; IR-BOTH-NEXT: ret
210 ; IR-BOTH-NEXT: ret
229 ; IR-BOTH-NEXT: ret
245 ; IR-BOTH-NEXT: ret
262 ; IR-BOTH-NEXT: ret
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dlower-aggr-copies.ll20 ; IR-LABEL: @memcpy_caller
21 ; IR: entry:
36 ; IR: ret i8* %dst
54 ; IR: entry:
69 ; IR: ret i8* %dst
103 ; IR: entry:
105 ; IR: load-store-loop:
122 ; IR-LABEL: @memset_caller
126 ; IR: loadstoreloop:
148 ; IR: loadstoreloop:
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/llvm-project-15.0.7/llvm/test/Other/
H A Dchange-printer.ll110 ; CHECK-SIMPLE: *** IR Dump At Start ***
122 ; CHECK-SIMPLE-NOT: *** IR
124 ; CHECK-FUNC-FILTER: *** IR Dump At Start ***
206 ; CHECK-SIMPLE-BEFORE-NOT: *** IR
233 ; CHECK-QUIET-SIMPLE-NOT: *** IR
238 ; CHECK-QUIET-FUNC-FILTER-NOT: *** IR
245 ; CHECK-QUIET-PRINT-MOD-SCOPE-NOT: *** IR
257 ; CHECK-QUIET-FILTER-MULT-FUNC-NOT: *** IR
259 ; CHECK-QUIET-FILTER-PASSES-NONE-NOT: *** IR
267 ; CHECK-QUIET-FILTER-PASSES-NOT: *** IR
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h124 CriticalPredecessor.IID = IR.getSourceIndex(); in onGroupIssued()
135 void onInstructionIssued(const InstRef &IR) { in onInstructionIssued() argument
140 const Instruction &IS = *IR.getInstruction(); in onInstructionIssued()
144 CriticalMemoryInstruction = IR; in onInstructionIssued()
146 CriticalMemoryInstruction = IR; in onInstructionIssued()
163 void onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted() argument
276 bool isReady(const InstRef &IR) const { in isReady() argument
284 bool isPending(const InstRef &IR) const { in isPending() argument
292 bool isWaiting(const InstRef &IR) const { in isWaiting() argument
330 Groups[GroupID]->onInstructionIssued(IR); in onInstructionIssued()
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/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVOps.td24 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
26 include "mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td"
27 include "mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td"
28 include "mlir/Dialect/SPIRV/IR/SPIRVBitOps.td"
29 include "mlir/Dialect/SPIRV/IR/SPIRVCastOps.td"
33 include "mlir/Dialect/SPIRV/IR/SPIRVGLOps.td"
34 include "mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td"
35 include "mlir/Dialect/SPIRV/IR/SPIRVImageOps.td"
37 include "mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td"
39 include "mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td"
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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-lsr-scaled-index-addressing-mode.ll14 ; IR-NEXT: entry:
16 ; IR: loop.ph:
22 ; IR: loop:
34 ; IR: loop.exit:
36 ; IR: exit:
37 ; IR-NEXT: ret void
87 ; IR-NEXT: entry:
89 ; IR: loop.ph:
97 ; IR: loop:
109 ; IR: loop.exit:
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/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DPassManagerImpl.h36 AnalysisManager<IRUnitT, ExtraArgTs...>::clear(IRUnitT &IR, in clear() argument
41 auto ResultsListI = AnalysisResultLists.find(&IR); in clear()
46 AnalysisResults.erase({IDAndResult.first, &IR}); in clear()
55 AnalysisKey *ID, IRUnitT &IR, ExtraArgTs... ExtraArgs) { in getResultImpl() argument
69 PI.runBeforeAnalysis(P, IR); in getResultImpl()
75 PI.runAfterAnalysis(P, IR); in getResultImpl()
79 RI = AnalysisResults.find({ID, &IR}); in getResultImpl()
90 IRUnitT &IR, const PreservedAnalyses &PA) { in invalidate() argument
135 PI->runAnalysisInvalidated(this->lookUpPass(ID), IR); in invalidate()
138 AnalysisResults.erase({ID, &IR}); in invalidate()
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/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Ddllstorage.m30 // CHECK-IR-DAG: @"OBJC_IVAR_$_J._ivar" = global i32
35 // CHECK-IR-DAG: @"OBJC_METACLASS_$_K" = dso_local global %struct._class_t
36 // CHECK-IR-DAG: @"OBJC_CLASS_$_K" = dso_local global %struct._class_t
46 // CHECK-IR-DAG: @"OBJC_IVAR_$_K._ivar" = global i32
75 // CHECK-IR-DAG: @"OBJC_IVAR_$_L._none" = global i32
76 // CHECK-IR-DAG: @"OBJC_IVAR_$_L._public" = dllexport global i32
77 // CHECK-IR-DAG: @"OBJC_IVAR_$_L._protected" = dllexport global i32
78 // CHECK-IR-DAG: @"OBJC_IVAR_$_L._package" = global i32
79 // CHECK-IR-DAG: @"OBJC_IVAR_$_L._private" = global i32
90 // CHECK-IR-DAG: @"OBJC_IVAR_$_M._ivar" = external dllimport global i32
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