1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_urem_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s0, 0, s12
16; GCN-NEXT:    s_subb_u32 s1, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    s_mov_b32 s5, s9
21; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
22; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
23; GCN-NEXT:    v_trunc_f32_e32 v1, v1
24; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
25; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
26; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
27; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
28; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
29; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
30; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
31; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
32; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
33; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
34; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
35; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
36; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
37; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
38; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
39; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
40; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
41; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
42; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
43; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
44; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
45; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
46; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
47; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
48; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
49; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
50; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
51; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
52; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
53; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
54; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
55; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
56; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
57; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
58; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
59; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
60; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
61; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
62; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
63; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
64; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
65; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
66; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
67; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
68; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
69; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
70; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
71; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
72; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
73; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
74; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
75; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
76; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
77; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
78; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
79; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
80; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
81; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
82; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
83; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
84; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
85; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
86; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
87; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
88; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
89; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
90; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
91; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
92; GCN-NEXT:    v_mov_b32_e32 v3, s13
93; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
94; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
95; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
96; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
97; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
98; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
99; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
100; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
101; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
102; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
103; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
104; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
105; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
106; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
107; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
108; GCN-NEXT:    v_mov_b32_e32 v5, s11
109; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
110; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
111; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
112; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
113; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
114; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
115; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
116; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
117; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
118; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
119; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
120; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
121; GCN-NEXT:    s_endpgm
122;
123; GCN-IR-LABEL: s_test_urem_i64:
124; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
125; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
126; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
127; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
128; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
129; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
130; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
131; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
132; GCN-IR-NEXT:    s_add_i32 s14, s12, 32
133; GCN-IR-NEXT:    s_or_b64 s[12:13], s[8:9], s[10:11]
134; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
135; GCN-IR-NEXT:    s_min_u32 s10, s14, s8
136; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
137; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
138; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s3
139; GCN-IR-NEXT:    s_min_u32 s14, s8, s9
140; GCN-IR-NEXT:    s_sub_u32 s8, s10, s14
141; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
142; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
143; GCN-IR-NEXT:    s_mov_b32 s11, 0
144; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[16:17]
145; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
146; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[12:13], -1
147; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
148; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
149; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
150; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
151; GCN-IR-NEXT:    s_add_u32 s12, s8, 1
152; GCN-IR-NEXT:    s_addc_u32 s13, s9, 0
153; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[12:13], 0
154; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
155; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[16:17]
156; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
157; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
158; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
159; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s12
160; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
161; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
162; GCN-IR-NEXT:    s_not_b64 s[6:7], s[10:11]
163; GCN-IR-NEXT:    s_add_u32 s10, s6, s14
164; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
165; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
166; GCN-IR-NEXT:    s_mov_b32 s7, 0
167; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
168; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
169; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
170; GCN-IR-NEXT:    s_lshr_b32 s6, s9, 31
171; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
172; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[6:7]
173; GCN-IR-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
174; GCN-IR-NEXT:    s_sub_u32 s6, s16, s12
175; GCN-IR-NEXT:    s_subb_u32 s6, s17, s13
176; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
177; GCN-IR-NEXT:    s_mov_b32 s15, s14
178; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
179; GCN-IR-NEXT:    s_and_b64 s[14:15], s[14:15], s[4:5]
180; GCN-IR-NEXT:    s_sub_u32 s12, s12, s14
181; GCN-IR-NEXT:    s_subb_u32 s13, s13, s15
182; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
183; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
184; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
185; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
186; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
187; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
188; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
189; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
190; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
191; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
192; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
193; GCN-IR-NEXT:    s_branch .LBB0_6
194; GCN-IR-NEXT:  .LBB0_5:
195; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
196; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
197; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
198; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
199; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
200; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
201; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
202; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
203; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
204; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
205; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
206; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
207; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
208; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
209; GCN-IR-NEXT:    s_mov_b32 s10, -1
210; GCN-IR-NEXT:    s_mov_b32 s8, s0
211; GCN-IR-NEXT:    s_mov_b32 s9, s1
212; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
213; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
214; GCN-IR-NEXT:    s_endpgm
215  %result = urem i64 %x, %y
216  store i64 %result, i64 addrspace(1)* %out
217  ret void
218}
219
220define i64 @v_test_urem_i64(i64 %x, i64 %y) {
221; GCN-LABEL: v_test_urem_i64:
222; GCN:       ; %bb.0:
223; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
224; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
225; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
226; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
227; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
228; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
229; GCN-NEXT:    v_rcp_f32_e32 v4, v4
230; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
231; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
232; GCN-NEXT:    v_trunc_f32_e32 v5, v5
233; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
234; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
235; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
236; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
237; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
238; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
239; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
240; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
241; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
242; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
243; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
244; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
245; GCN-NEXT:    v_mul_hi_u32 v13, v5, v8
246; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
247; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
248; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
249; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
250; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
251; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
252; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
253; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v13, vcc
254; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
255; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
256; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
257; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
258; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
259; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
260; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
261; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
262; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
263; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
264; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
265; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
266; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
267; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
268; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
269; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
270; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
271; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
272; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
273; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
274; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
275; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
276; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
277; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
278; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
279; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
280; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
281; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
282; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
283; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
284; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
285; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
286; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
287; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
288; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
289; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
290; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
291; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v9, vcc
292; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
293; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
294; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
295; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
296; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
297; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
298; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
299; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
300; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v1, v5
301; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
302; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
303; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v0, v2
304; GCN-NEXT:    v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
305; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
306; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
307; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
308; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
309; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
310; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
311; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
312; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
313; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
314; GCN-NEXT:    v_sub_i32_e64 v9, s[4:5], v6, v2
315; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
316; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
317; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
318; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
319; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
320; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
321; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
322; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
323; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
324; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v4, s[4:5]
325; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
326; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
327; GCN-NEXT:    s_setpc_b64 s[30:31]
328;
329; GCN-IR-LABEL: v_test_urem_i64:
330; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
331; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
332; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
333; GCN-IR-NEXT:    v_add_i32_e64 v4, s[6:7], 32, v4
334; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
335; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
336; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
337; GCN-IR-NEXT:    v_add_i32_e64 v4, s[6:7], 32, v4
338; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
339; GCN-IR-NEXT:    v_min_u32_e32 v9, v4, v5
340; GCN-IR-NEXT:    v_sub_i32_e64 v5, s[6:7], v8, v9
341; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
342; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
343; GCN-IR-NEXT:    v_subb_u32_e64 v6, s[6:7], 0, 0, s[6:7]
344; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[6:7], 63, v[5:6]
345; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
346; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
347; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[5:6]
348; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
349; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
350; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
351; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
352; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
353; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
354; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
355; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v5
356; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v6, vcc
357; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v5
358; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[10:11]
359; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
360; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
361; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
362; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
363; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
364; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
365; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
366; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v2
367; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v3, vcc
368; GCN-IR-NEXT:    v_not_b32_e32 v7, v8
369; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v10
370; GCN-IR-NEXT:    v_not_b32_e32 v6, 0
371; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, v7, v9
372; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
373; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v6, vcc
374; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
375; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
376; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
377; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
378; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
379; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
380; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
381; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
382; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
383; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
384; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
385; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
386; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
387; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v8
388; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
389; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
390; GCN-IR-NEXT:    v_and_b32_e32 v13, v12, v3
391; GCN-IR-NEXT:    v_and_b32_e32 v12, v12, v2
392; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
393; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
394; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v12
395; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
396; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
397; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
398; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
399; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
400; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
401; GCN-IR-NEXT:  ; %bb.4: ; %Flow
402; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
403; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
404; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
405; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
406; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
407; GCN-IR-NEXT:    v_or_b32_e32 v4, v6, v4
408; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
409; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
410; GCN-IR-NEXT:    v_mul_lo_u32 v5, v2, v7
411; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
412; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
413; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
414; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
415; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
416; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
417; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
418; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
419  %result = urem i64 %x, %y
420  ret i64 %result
421}
422
423define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
424; GCN-LABEL: s_test_urem31_i64:
425; GCN:       ; %bb.0:
426; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
427; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
428; GCN-NEXT:    s_waitcnt lgkmcnt(0)
429; GCN-NEXT:    s_mov_b32 s2, -1
430; GCN-NEXT:    s_lshr_b32 s4, s4, 1
431; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
432; GCN-NEXT:    s_lshr_b32 s5, s3, 1
433; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
434; GCN-NEXT:    s_mov_b32 s3, 0xf000
435; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
436; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
437; GCN-NEXT:    v_trunc_f32_e32 v2, v2
438; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
439; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
440; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
441; GCN-NEXT:    v_mov_b32_e32 v1, 0
442; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
443; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
444; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
445; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
446; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
447; GCN-NEXT:    s_endpgm
448;
449; GCN-IR-LABEL: s_test_urem31_i64:
450; GCN-IR:       ; %bb.0:
451; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
452; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
453; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
454; GCN-IR-NEXT:    s_mov_b32 s2, -1
455; GCN-IR-NEXT:    s_lshr_b32 s4, s4, 1
456; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
457; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 1
458; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
459; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
460; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
461; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
462; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
463; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
464; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
465; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
466; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
467; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
468; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
469; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
470; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
471; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
472; GCN-IR-NEXT:    s_endpgm
473  %1 = lshr i64 %x, 33
474  %2 = lshr i64 %y, 33
475  %result = urem i64 %1, %2
476  store i64 %result, i64 addrspace(1)* %out
477  ret void
478}
479
480define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
481; GCN-LABEL: s_test_urem31_v2i64:
482; GCN:       ; %bb.0:
483; GCN-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
484; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
485; GCN-NEXT:    v_mov_b32_e32 v1, 0
486; GCN-NEXT:    s_mov_b32 s3, 0xf000
487; GCN-NEXT:    s_mov_b32 s2, -1
488; GCN-NEXT:    s_waitcnt lgkmcnt(0)
489; GCN-NEXT:    s_lshr_b32 s4, s9, 1
490; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
491; GCN-NEXT:    s_lshr_b32 s5, s5, 1
492; GCN-NEXT:    s_lshr_b32 s6, s7, 1
493; GCN-NEXT:    s_lshr_b32 s7, s11, 1
494; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s5
495; GCN-NEXT:    v_rcp_iflag_f32_e32 v3, v0
496; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s7
497; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s6
498; GCN-NEXT:    v_mul_f32_e32 v3, v2, v3
499; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v4
500; GCN-NEXT:    v_trunc_f32_e32 v3, v3
501; GCN-NEXT:    v_mad_f32 v2, -v3, v0, v2
502; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
503; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
504; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
505; GCN-NEXT:    v_trunc_f32_e32 v2, v2
506; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
507; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
508; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v5
509; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
510; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
511; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
512; GCN-NEXT:    v_mul_lo_u32 v2, v2, s7
513; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
514; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
515; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
516; GCN-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v2
517; GCN-NEXT:    v_mov_b32_e32 v3, v1
518; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
519; GCN-NEXT:    s_endpgm
520;
521; GCN-IR-LABEL: s_test_urem31_v2i64:
522; GCN-IR:       ; %bb.0:
523; GCN-IR-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
524; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
525; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
526; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
527; GCN-IR-NEXT:    s_mov_b32 s2, -1
528; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
529; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 1
530; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
531; GCN-IR-NEXT:    s_lshr_b32 s5, s5, 1
532; GCN-IR-NEXT:    s_lshr_b32 s6, s7, 1
533; GCN-IR-NEXT:    s_lshr_b32 s7, s11, 1
534; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v2, s5
535; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v3, v0
536; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s7
537; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s6
538; GCN-IR-NEXT:    v_mul_f32_e32 v3, v2, v3
539; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v4
540; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
541; GCN-IR-NEXT:    v_mad_f32 v2, -v3, v0, v2
542; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v3
543; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
544; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
545; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
546; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
547; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
548; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v5
549; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
550; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
551; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
552; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s7
553; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
554; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
555; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
556; GCN-IR-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v2
557; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
558; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
559; GCN-IR-NEXT:    s_endpgm
560  %1 = lshr <2 x i64> %x, <i64 33, i64 33>
561  %2 = lshr <2 x i64> %y, <i64 33, i64 33>
562  %result = urem <2 x i64> %1, %2
563  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
564  ret void
565}
566
567define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
568; GCN-LABEL: s_test_urem24_i64:
569; GCN:       ; %bb.0:
570; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
571; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
572; GCN-NEXT:    s_waitcnt lgkmcnt(0)
573; GCN-NEXT:    s_mov_b32 s2, -1
574; GCN-NEXT:    s_lshr_b32 s4, s4, 8
575; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
576; GCN-NEXT:    s_lshr_b32 s5, s3, 8
577; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
578; GCN-NEXT:    s_mov_b32 s3, 0xf000
579; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
580; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
581; GCN-NEXT:    v_trunc_f32_e32 v2, v2
582; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
583; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
584; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
585; GCN-NEXT:    v_mov_b32_e32 v1, 0
586; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
587; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
588; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
589; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
590; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
591; GCN-NEXT:    s_endpgm
592;
593; GCN-IR-LABEL: s_test_urem24_i64:
594; GCN-IR:       ; %bb.0:
595; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
596; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
597; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
598; GCN-IR-NEXT:    s_mov_b32 s2, -1
599; GCN-IR-NEXT:    s_lshr_b32 s4, s4, 8
600; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
601; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 8
602; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
603; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
604; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
605; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
606; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
607; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
608; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
609; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
610; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
611; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
612; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
613; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
614; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
615; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
616; GCN-IR-NEXT:    s_endpgm
617  %1 = lshr i64 %x, 40
618  %2 = lshr i64 %y, 40
619  %result = urem i64 %1, %2
620  store i64 %result, i64 addrspace(1)* %out
621  ret void
622}
623
624define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
625; GCN-LABEL: s_test_urem23_64_v2i64:
626; GCN:       ; %bb.0:
627; GCN-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
628; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
629; GCN-NEXT:    v_mov_b32_e32 v1, 0
630; GCN-NEXT:    s_mov_b32 s3, 0xf000
631; GCN-NEXT:    s_mov_b32 s2, -1
632; GCN-NEXT:    s_waitcnt lgkmcnt(0)
633; GCN-NEXT:    s_lshr_b32 s4, s9, 1
634; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
635; GCN-NEXT:    s_lshr_b32 s5, s5, 1
636; GCN-NEXT:    s_lshr_b32 s6, s7, 9
637; GCN-NEXT:    s_lshr_b32 s7, s11, 9
638; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s5
639; GCN-NEXT:    v_rcp_iflag_f32_e32 v3, v0
640; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s7
641; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s6
642; GCN-NEXT:    v_mul_f32_e32 v3, v2, v3
643; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v4
644; GCN-NEXT:    v_trunc_f32_e32 v3, v3
645; GCN-NEXT:    v_mad_f32 v2, -v3, v0, v2
646; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
647; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
648; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
649; GCN-NEXT:    v_trunc_f32_e32 v2, v2
650; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
651; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
652; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v5
653; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
654; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
655; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
656; GCN-NEXT:    v_mul_lo_u32 v2, v2, s7
657; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
658; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
659; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
660; GCN-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v2
661; GCN-NEXT:    v_mov_b32_e32 v3, v1
662; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
663; GCN-NEXT:    s_endpgm
664;
665; GCN-IR-LABEL: s_test_urem23_64_v2i64:
666; GCN-IR:       ; %bb.0:
667; GCN-IR-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
668; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
669; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
670; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
671; GCN-IR-NEXT:    s_mov_b32 s2, -1
672; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
673; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 1
674; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
675; GCN-IR-NEXT:    s_lshr_b32 s5, s5, 1
676; GCN-IR-NEXT:    s_lshr_b32 s6, s7, 9
677; GCN-IR-NEXT:    s_lshr_b32 s7, s11, 9
678; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v2, s5
679; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v3, v0
680; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s7
681; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s6
682; GCN-IR-NEXT:    v_mul_f32_e32 v3, v2, v3
683; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v4
684; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
685; GCN-IR-NEXT:    v_mad_f32 v2, -v3, v0, v2
686; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v3
687; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
688; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
689; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
690; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
691; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
692; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v5
693; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
694; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
695; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
696; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s7
697; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
698; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
699; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
700; GCN-IR-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v2
701; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
702; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
703; GCN-IR-NEXT:    s_endpgm
704  %1 = lshr <2 x i64> %x, <i64 33, i64 41>
705  %2 = lshr <2 x i64> %y, <i64 33, i64 41>
706  %result = urem <2 x i64> %1, %2
707  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
708  ret void
709}
710
711define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
712; GCN-LABEL: s_test_urem_k_num_i64:
713; GCN:       ; %bb.0:
714; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
715; GCN-NEXT:    s_mov_b32 s11, 0xf000
716; GCN-NEXT:    s_mov_b32 s10, -1
717; GCN-NEXT:    s_waitcnt lgkmcnt(0)
718; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
719; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
720; GCN-NEXT:    s_sub_u32 s0, 0, s6
721; GCN-NEXT:    s_subb_u32 s1, 0, s7
722; GCN-NEXT:    s_mov_b32 s8, s4
723; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
724; GCN-NEXT:    v_rcp_f32_e32 v0, v0
725; GCN-NEXT:    s_mov_b32 s9, s5
726; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
727; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
728; GCN-NEXT:    v_trunc_f32_e32 v1, v1
729; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
730; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
731; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
732; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
733; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
734; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
735; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
736; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
737; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
738; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
739; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
740; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
741; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
742; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
743; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
744; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
745; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
746; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
747; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
748; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
749; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v8, vcc
750; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
751; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
752; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
753; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
754; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
755; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
756; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
757; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
758; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
759; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
760; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
761; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
762; GCN-NEXT:    v_mul_hi_u32 v8, v0, v2
763; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
764; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
765; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
766; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
767; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
768; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
769; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
770; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v5, vcc
771; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
772; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
773; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
774; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
775; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
776; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
777; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
778; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
779; GCN-NEXT:    v_mov_b32_e32 v3, s7
780; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
781; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
782; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
783; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
784; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
785; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
786; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
787; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
788; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
789; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s6, v0
790; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
791; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s7, v5
792; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
793; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s6, v4
794; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
795; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
796; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s7, v5
797; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s6, v4
798; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
799; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
800; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
801; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
802; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
803; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
804; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
805; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
806; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
807; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
808; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
809; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
810; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
811; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
812; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
813; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
814; GCN-NEXT:    s_endpgm
815;
816; GCN-IR-LABEL: s_test_urem_k_num_i64:
817; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
818; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
819; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
820; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
821; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
822; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
823; GCN-IR-NEXT:    s_min_u32 s8, s4, s5
824; GCN-IR-NEXT:    s_add_u32 s6, s8, 0xffffffc5
825; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
826; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
827; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
828; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
829; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
830; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
831; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
832; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
833; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
834; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_5
835; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
836; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
837; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
838; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
839; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
840; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[12:13]
841; GCN-IR-NEXT:    s_lshl_b64 s[6:7], 24, s6
842; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_4
843; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
844; GCN-IR-NEXT:    s_lshr_b64 s[10:11], 24, s10
845; GCN-IR-NEXT:    s_add_u32 s14, s2, -1
846; GCN-IR-NEXT:    s_addc_u32 s15, s3, -1
847; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
848; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
849; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
850; GCN-IR-NEXT:    s_mov_b32 s5, 0
851; GCN-IR-NEXT:  .LBB6_3: ; %udiv-do-while
852; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
853; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
854; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
855; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
856; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
857; GCN-IR-NEXT:    s_or_b64 s[6:7], s[12:13], s[6:7]
858; GCN-IR-NEXT:    s_sub_u32 s4, s14, s10
859; GCN-IR-NEXT:    s_subb_u32 s4, s15, s11
860; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
861; GCN-IR-NEXT:    s_mov_b32 s13, s12
862; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
863; GCN-IR-NEXT:    s_and_b64 s[12:13], s[12:13], s[2:3]
864; GCN-IR-NEXT:    s_sub_u32 s10, s10, s12
865; GCN-IR-NEXT:    s_subb_u32 s11, s11, s13
866; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
867; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
868; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
869; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
870; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
871; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_3
872; GCN-IR-NEXT:  .LBB6_4: ; %Flow5
873; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
874; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
875; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
876; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
877; GCN-IR-NEXT:    s_branch .LBB6_6
878; GCN-IR-NEXT:  .LBB6_5:
879; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
880; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
881; GCN-IR-NEXT:  .LBB6_6: ; %udiv-end
882; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
883; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
884; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
885; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
886; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
887; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
888; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
889; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
890; GCN-IR-NEXT:    s_mov_b32 s6, -1
891; GCN-IR-NEXT:    s_mov_b32 s4, s0
892; GCN-IR-NEXT:    s_mov_b32 s5, s1
893; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
894; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
895; GCN-IR-NEXT:    s_endpgm
896  %result = urem i64 24, %x
897  store i64 %result, i64 addrspace(1)* %out
898  ret void
899}
900
901define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
902; GCN-LABEL: s_test_urem_k_den_i64:
903; GCN:       ; %bb.0:
904; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
905; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
906; GCN-NEXT:    v_rcp_f32_e32 v0, v0
907; GCN-NEXT:    s_movk_i32 s4, 0xffe8
908; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
909; GCN-NEXT:    s_mov_b32 s7, 0xf000
910; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
911; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
912; GCN-NEXT:    v_trunc_f32_e32 v1, v1
913; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
914; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
915; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
916; GCN-NEXT:    s_waitcnt lgkmcnt(0)
917; GCN-NEXT:    s_mov_b32 s5, s1
918; GCN-NEXT:    s_mov_b32 s6, -1
919; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
920; GCN-NEXT:    v_mul_lo_u32 v4, v1, s4
921; GCN-NEXT:    v_mul_lo_u32 v3, v0, s4
922; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v0
923; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
924; GCN-NEXT:    v_mul_hi_u32 v5, v0, v3
925; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
926; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
927; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
928; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
929; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
930; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
931; GCN-NEXT:    v_mul_lo_u32 v6, v1, v3
932; GCN-NEXT:    v_mul_hi_u32 v3, v1, v3
933; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
934; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
935; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
936; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
937; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
938; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
939; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
940; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
941; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
942; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
943; GCN-NEXT:    s_mov_b32 s4, s0
944; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v0
945; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
946; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
947; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
948; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
949; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
950; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
951; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
952; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
953; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
954; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
955; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
956; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
957; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v7, vcc
958; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
959; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
960; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
961; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
962; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
963; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
964; GCN-NEXT:    v_mul_hi_u32 v4, s2, v1
965; GCN-NEXT:    v_mul_hi_u32 v5, s3, v1
966; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
967; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
968; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
969; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
970; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
971; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
972; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
973; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
974; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
975; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
976; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
977; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
978; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
979; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
980; GCN-NEXT:    v_mov_b32_e32 v2, s3
981; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
982; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
983; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
984; GCN-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
985; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
986; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
987; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v2
988; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
989; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
990; GCN-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
991; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
992; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v0
993; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
994; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
995; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
996; GCN-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
997; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
998; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
999; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1000; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1001; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1002; GCN-NEXT:    s_endpgm
1003;
1004; GCN-IR-LABEL: s_test_urem_k_den_i64:
1005; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1006; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1007; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1008; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1009; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1010; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1011; GCN-IR-NEXT:    s_min_u32 s8, s4, s5
1012; GCN-IR-NEXT:    s_sub_u32 s6, 59, s8
1013; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1014; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1015; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1016; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1017; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1018; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1019; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1020; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1021; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1022; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_5
1023; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1024; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
1025; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
1026; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
1027; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1028; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[12:13]
1029; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
1030; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_4
1031; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1032; GCN-IR-NEXT:    s_lshr_b64 s[10:11], s[2:3], s10
1033; GCN-IR-NEXT:    s_add_u32 s8, s8, 0xffffffc4
1034; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1035; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1036; GCN-IR-NEXT:    s_mov_b32 s5, 0
1037; GCN-IR-NEXT:  .LBB7_3: ; %udiv-do-while
1038; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1039; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1040; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
1041; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1042; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
1043; GCN-IR-NEXT:    s_or_b64 s[6:7], s[12:13], s[6:7]
1044; GCN-IR-NEXT:    s_sub_u32 s4, 23, s10
1045; GCN-IR-NEXT:    s_subb_u32 s4, 0, s11
1046; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
1047; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
1048; GCN-IR-NEXT:    s_and_b32 s12, s12, 24
1049; GCN-IR-NEXT:    s_sub_u32 s10, s10, s12
1050; GCN-IR-NEXT:    s_subb_u32 s11, s11, 0
1051; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1052; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1053; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[8:9], 0
1054; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
1055; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
1056; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_3
1057; GCN-IR-NEXT:  .LBB7_4: ; %Flow5
1058; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1059; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
1060; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1061; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
1062; GCN-IR-NEXT:    s_branch .LBB7_6
1063; GCN-IR-NEXT:  .LBB7_5:
1064; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1065; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1066; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1067; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1068; GCN-IR-NEXT:  .LBB7_6: ; %udiv-end
1069; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, 24
1070; GCN-IR-NEXT:    v_mul_hi_u32 v2, v0, 24
1071; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, 24
1072; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1073; GCN-IR-NEXT:    s_mov_b32 s6, -1
1074; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
1075; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1076; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1077; GCN-IR-NEXT:    s_mov_b32 s4, s0
1078; GCN-IR-NEXT:    s_mov_b32 s5, s1
1079; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1080; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1081; GCN-IR-NEXT:    s_endpgm
1082  %result = urem i64 %x, 24
1083  store i64 %result, i64 addrspace(1)* %out
1084  ret void
1085}
1086
1087; FIXME: Constant bus violation
1088; define i64 @v_test_urem_k_num_i64(i64 %x) {
1089;   %result = urem i64 24, %x
1090;   ret i64 %result
1091; }
1092
1093define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
1094; GCN-LABEL: v_test_urem_pow2_k_num_i64:
1095; GCN:       ; %bb.0:
1096; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1097; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1098; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1099; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1100; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1101; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1102; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1103; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1104; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1105; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1106; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1107; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1108; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1109; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1110; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1111; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1112; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1113; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1114; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1115; GCN-NEXT:    v_mul_hi_u32 v7, v2, v9
1116; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1117; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1118; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
1119; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1120; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1121; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v10, vcc
1122; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1123; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1124; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
1125; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v9, vcc
1126; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v11, vcc
1127; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1128; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1129; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1130; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1131; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1132; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1133; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1134; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1135; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1136; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1137; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1138; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1139; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1140; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1141; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1142; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1143; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1144; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1145; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1146; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1147; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1148; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
1149; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1150; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1151; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1152; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1153; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1154; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1155; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1156; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1157; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1158; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1159; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1160; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1161; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1162; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1163; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1164; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1165; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1166; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1167; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1168; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1169; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1170; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1171; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1172; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1173; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1174; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1175; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1176; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1177; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1178; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1179; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1180; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1181; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1182; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1183; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1184; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1185; GCN-NEXT:    s_setpc_b64 s[30:31]
1186;
1187; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1188; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1189; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1190; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1191; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1192; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1193; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1194; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 0xffffffd0, v6
1195; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1196; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1197; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1198; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0x8000
1199; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1200; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1201; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s[4:5]
1202; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1203; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1204; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1205; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1206; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1207; GCN-IR-NEXT:    s_cbranch_execz .LBB8_6
1208; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1209; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v3
1210; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v4, vcc
1211; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1212; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[7:8]
1213; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1214; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1215; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1216; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1217; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1218; GCN-IR-NEXT:    s_cbranch_execz .LBB8_5
1219; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1220; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1221; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1222; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1223; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v7
1224; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1225; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1226; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
1227; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1228; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1229; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1230; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1231; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1232; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1233; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1234; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1235; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1236; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1237; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1238; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1239; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1240; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1241; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1242; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1243; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v1
1244; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v0
1245; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1246; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1247; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1248; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1249; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1250; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1251; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1252; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1253; GCN-IR-NEXT:    s_cbranch_execnz .LBB8_3
1254; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1255; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1256; GCN-IR-NEXT:  .LBB8_5: ; %Flow3
1257; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1258; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[2:3], 1
1259; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v7
1260; GCN-IR-NEXT:    v_or_b32_e32 v5, v4, v6
1261; GCN-IR-NEXT:  .LBB8_6: ; %Flow4
1262; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1263; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v2
1264; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v5
1265; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v5
1266; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v5
1267; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1268; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1269; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1270; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1271; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1272  %result = urem i64 32768, %x
1273  ret i64 %result
1274}
1275
1276define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
1277; GCN-LABEL: v_test_urem_pow2_k_den_i64:
1278; GCN:       ; %bb.0:
1279; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1280; GCN-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
1281; GCN-NEXT:    v_mov_b32_e32 v1, 0
1282; GCN-NEXT:    s_setpc_b64 s[30:31]
1283;
1284; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1285; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1286; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1287; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1288; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1289; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1290; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1291; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 48, v6
1292; GCN-IR-NEXT:    v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1293; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1294; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1295; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1296; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1297; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1298; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1299; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1300; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1301; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1302; GCN-IR-NEXT:    s_cbranch_execz .LBB9_6
1303; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1304; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1305; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1306; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1307; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[7:8]
1308; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1309; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1310; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1311; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1312; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1313; GCN-IR-NEXT:    s_cbranch_execz .LBB9_5
1314; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1315; GCN-IR-NEXT:    v_lshr_b64 v[8:9], v[0:1], v7
1316; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffcf, v6
1317; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1318; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1319; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1320; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1321; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1322; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1323; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1324; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1325; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1326; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1327; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1328; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v8
1329; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1330; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v9, vcc
1331; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1332; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1333; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1334; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1335; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1336; GCN-IR-NEXT:    v_and_b32_e32 v10, 0x8000, v10
1337; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1338; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1339; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1340; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1341; GCN-IR-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
1342; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1343; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1344; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1345; GCN-IR-NEXT:    s_cbranch_execnz .LBB9_3
1346; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1347; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1348; GCN-IR-NEXT:  .LBB9_5: ; %Flow3
1349; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1350; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1351; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1352; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1353; GCN-IR-NEXT:  .LBB9_6: ; %Flow4
1354; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1355; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[4:5], 15
1356; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1357; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1358; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1359  %result = urem i64 %x, 32768
1360  ret i64 %result
1361}
1362
1363define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1364; GCN-LABEL: s_test_urem24_k_num_i64:
1365; GCN:       ; %bb.0:
1366; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1367; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
1368; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1369; GCN-NEXT:    s_mov_b32 s2, -1
1370; GCN-NEXT:    s_lshr_b32 s4, s3, 8
1371; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
1372; GCN-NEXT:    s_mov_b32 s3, 0xf000
1373; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1374; GCN-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1
1375; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1376; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1377; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
1378; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1379; GCN-NEXT:    v_mov_b32_e32 v1, 0
1380; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1381; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1382; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1383; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1384; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1385; GCN-NEXT:    s_endpgm
1386;
1387; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1388; GCN-IR:       ; %bb.0:
1389; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1390; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
1391; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1392; GCN-IR-NEXT:    s_mov_b32 s2, -1
1393; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
1394; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
1395; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1396; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1397; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x41c00000, v1
1398; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1399; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1400; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
1401; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1402; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1403; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1404; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
1405; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1406; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1407; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1408; GCN-IR-NEXT:    s_endpgm
1409  %x.shr = lshr i64 %x, 40
1410  %result = urem i64 24, %x.shr
1411  store i64 %result, i64 addrspace(1)* %out
1412  ret void
1413}
1414
1415define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1416; GCN-LABEL: s_test_urem24_k_den_i64:
1417; GCN:       ; %bb.0:
1418; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1419; GCN-NEXT:    s_movk_i32 s4, 0x5b7f
1420; GCN-NEXT:    s_mov_b32 s7, 0xf000
1421; GCN-NEXT:    s_mov_b32 s6, -1
1422; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1423; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1424; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1425; GCN-NEXT:    s_mov_b32 s3, 0x46b6fe00
1426; GCN-NEXT:    s_mov_b32 s5, s1
1427; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1428; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1429; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1430; GCN-NEXT:    v_mad_f32 v0, -v1, s3, v0
1431; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s3
1432; GCN-NEXT:    v_mov_b32_e32 v1, 0
1433; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1434; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1435; GCN-NEXT:    s_mov_b32 s4, s0
1436; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1437; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1438; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1439; GCN-NEXT:    s_endpgm
1440;
1441; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1442; GCN-IR:       ; %bb.0:
1443; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1444; GCN-IR-NEXT:    s_movk_i32 s4, 0x5b7f
1445; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1446; GCN-IR-NEXT:    s_mov_b32 s6, -1
1447; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1448; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1449; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1450; GCN-IR-NEXT:    s_mov_b32 s3, 0x46b6fe00
1451; GCN-IR-NEXT:    s_mov_b32 s5, s1
1452; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1453; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1454; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1455; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s3, v0
1456; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s3
1457; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1458; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1459; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
1460; GCN-IR-NEXT:    s_mov_b32 s4, s0
1461; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1462; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1463; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1464; GCN-IR-NEXT:    s_endpgm
1465  %x.shr = lshr i64 %x, 40
1466  %result = urem i64 %x.shr, 23423
1467  store i64 %result, i64 addrspace(1)* %out
1468  ret void
1469}
1470
1471define i64 @v_test_urem24_k_num_i64(i64 %x) {
1472; GCN-LABEL: v_test_urem24_k_num_i64:
1473; GCN:       ; %bb.0:
1474; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1475; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1476; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1477; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1478; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1479; GCN-NEXT:    v_mul_f32_e32 v2, 0x41c00000, v2
1480; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1481; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1482; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1483; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1484; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1485; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1486; GCN-NEXT:    v_mov_b32_e32 v1, 0
1487; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1488; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1489; GCN-NEXT:    s_setpc_b64 s[30:31]
1490;
1491; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1492; GCN-IR:       ; %bb.0:
1493; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1494; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1495; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1496; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1497; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1498; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x41c00000, v2
1499; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1500; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1501; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1502; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1503; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1504; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1505; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1506; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1507; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1508; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1509  %x.shr = lshr i64 %x, 40
1510  %result = urem i64 24, %x.shr
1511  ret i64 %result
1512}
1513
1514define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
1515; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
1516; GCN:       ; %bb.0:
1517; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1518; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1519; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1520; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1521; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1522; GCN-NEXT:    v_mul_f32_e32 v2, 0x47000000, v2
1523; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1524; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1525; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1526; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1527; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1528; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1529; GCN-NEXT:    v_mov_b32_e32 v1, 0
1530; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1531; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1532; GCN-NEXT:    s_setpc_b64 s[30:31]
1533;
1534; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1535; GCN-IR:       ; %bb.0:
1536; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1537; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1538; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1539; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1540; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1541; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x47000000, v2
1542; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1543; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1544; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1545; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1546; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1547; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1548; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1549; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1550; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1551; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1552  %x.shr = lshr i64 %x, 40
1553  %result = urem i64 32768, %x.shr
1554  ret i64 %result
1555}
1556
1557define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
1558; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
1559; GCN:       ; %bb.0:
1560; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1561; GCN-NEXT:    v_bfe_u32 v0, v1, 8, 15
1562; GCN-NEXT:    v_mov_b32_e32 v1, 0
1563; GCN-NEXT:    s_setpc_b64 s[30:31]
1564;
1565; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1566; GCN-IR:       ; %bb.0:
1567; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1568; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1569; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1570; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1571; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
1572; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1573; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1574; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
1575; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
1576; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1577; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
1578; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
1579; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1580; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1581; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1582  %x.shr = lshr i64 %x, 40
1583  %result = urem i64 %x.shr, 32768
1584  ret i64 %result
1585}
1586