Lines Matching refs:IR
3 … -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
123 ; GCN-IR-LABEL: s_test_urem_i64:
124 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
125 ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
126 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
127 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
128 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
129 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
130 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
131 ; GCN-IR-NEXT: s_flbit_i32_b32 s12, s4
132 ; GCN-IR-NEXT: s_add_i32 s14, s12, 32
133 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[8:9], s[10:11]
134 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s5
135 ; GCN-IR-NEXT: s_min_u32 s10, s14, s8
136 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2
137 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
138 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3
139 ; GCN-IR-NEXT: s_min_u32 s14, s8, s9
140 ; GCN-IR-NEXT: s_sub_u32 s8, s10, s14
141 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
142 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
143 ; GCN-IR-NEXT: s_mov_b32 s11, 0
144 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[16:17]
145 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
146 ; GCN-IR-NEXT: s_xor_b64 s[18:19], s[12:13], -1
147 ; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17]
148 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
149 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
150 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
151 ; GCN-IR-NEXT: s_add_u32 s12, s8, 1
152 ; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
153 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 0
154 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
155 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17]
156 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
157 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
158 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
159 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s12
160 ; GCN-IR-NEXT: s_add_u32 s16, s4, -1
161 ; GCN-IR-NEXT: s_addc_u32 s17, s5, -1
162 ; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11]
163 ; GCN-IR-NEXT: s_add_u32 s10, s6, s14
164 ; GCN-IR-NEXT: s_addc_u32 s11, s7, 0
165 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
166 ; GCN-IR-NEXT: s_mov_b32 s7, 0
167 ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
168 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
169 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
170 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
171 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
172 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
173 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
174 ; GCN-IR-NEXT: s_sub_u32 s6, s16, s12
175 ; GCN-IR-NEXT: s_subb_u32 s6, s17, s13
176 ; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31
177 ; GCN-IR-NEXT: s_mov_b32 s15, s14
178 ; GCN-IR-NEXT: s_and_b32 s6, s14, 1
179 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[4:5]
180 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s14
181 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s15
182 ; GCN-IR-NEXT: s_add_u32 s10, s10, 1
183 ; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
184 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
185 ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7]
186 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
187 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
188 ; GCN-IR-NEXT: .LBB0_4: ; %Flow6
189 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
190 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
191 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
192 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
193 ; GCN-IR-NEXT: s_branch .LBB0_6
194 ; GCN-IR-NEXT: .LBB0_5:
195 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
196 ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[12:13]
197 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
198 ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[12:13]
199 ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
200 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s4, v1
201 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s4, v0
202 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s5, v0
203 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s4, v0
204 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
205 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v2
206 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1
207 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
208 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
209 ; GCN-IR-NEXT: s_mov_b32 s10, -1
210 ; GCN-IR-NEXT: s_mov_b32 s8, s0
211 ; GCN-IR-NEXT: s_mov_b32 s9, s1
212 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
213 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
214 ; GCN-IR-NEXT: s_endpgm
329 ; GCN-IR-LABEL: v_test_urem_i64:
330 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
331 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
332 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
333 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
334 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
335 ; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
336 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
337 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
338 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
339 ; GCN-IR-NEXT: v_min_u32_e32 v9, v4, v5
340 ; GCN-IR-NEXT: v_sub_i32_e64 v5, s[6:7], v8, v9
341 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
342 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
343 ; GCN-IR-NEXT: v_subb_u32_e64 v6, s[6:7], 0, 0, s[6:7]
344 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[5:6]
345 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
346 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
347 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6]
348 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
349 ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
350 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
351 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
352 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
353 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
354 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
355 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v5
356 ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v6, vcc
357 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5
358 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
359 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
360 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
361 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
362 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
363 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
364 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
365 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
366 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
367 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
368 ; GCN-IR-NEXT: v_not_b32_e32 v7, v8
369 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v10
370 ; GCN-IR-NEXT: v_not_b32_e32 v6, 0
371 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v9
372 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
373 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc
374 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
375 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
376 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
377 ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
378 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
379 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
380 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
381 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
382 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
383 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
384 ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
385 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
386 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
387 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
388 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
389 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
390 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3
391 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2
392 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
393 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
394 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
395 ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
396 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
397 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
398 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
399 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
400 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
401 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
402 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
403 ; GCN-IR-NEXT: .LBB1_5: ; %Flow3
404 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
405 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
406 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
407 ; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v4
408 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
409 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
410 ; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7
411 ; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4
412 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4
413 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4
414 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5
415 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3
416 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
417 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
418 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
449 ; GCN-IR-LABEL: s_test_urem31_i64:
450 ; GCN-IR: ; %bb.0:
451 ; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe
452 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
453 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
454 ; GCN-IR-NEXT: s_mov_b32 s2, -1
455 ; GCN-IR-NEXT: s_lshr_b32 s4, s4, 1
456 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
457 ; GCN-IR-NEXT: s_lshr_b32 s5, s3, 1
458 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5
459 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
460 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
461 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
462 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
463 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
464 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
465 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
466 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
467 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
468 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
469 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
470 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
471 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
472 ; GCN-IR-NEXT: s_endpgm
521 ; GCN-IR-LABEL: s_test_urem31_v2i64:
522 ; GCN-IR: ; %bb.0:
523 ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
524 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
525 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
526 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
527 ; GCN-IR-NEXT: s_mov_b32 s2, -1
528 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
529 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1
530 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
531 ; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1
532 ; GCN-IR-NEXT: s_lshr_b32 s6, s7, 1
533 ; GCN-IR-NEXT: s_lshr_b32 s7, s11, 1
534 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5
535 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0
536 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7
537 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6
538 ; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3
539 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4
540 ; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3
541 ; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2
542 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3
543 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
544 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6
545 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
546 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
547 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
548 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5
549 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
550 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
551 ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
552 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7
553 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
554 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
555 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
556 ; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
557 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
558 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
559 ; GCN-IR-NEXT: s_endpgm
593 ; GCN-IR-LABEL: s_test_urem24_i64:
594 ; GCN-IR: ; %bb.0:
595 ; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe
596 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
597 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
598 ; GCN-IR-NEXT: s_mov_b32 s2, -1
599 ; GCN-IR-NEXT: s_lshr_b32 s4, s4, 8
600 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
601 ; GCN-IR-NEXT: s_lshr_b32 s5, s3, 8
602 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5
603 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
604 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
605 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
606 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
607 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
608 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
609 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
610 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
611 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
612 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
613 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
614 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
615 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
616 ; GCN-IR-NEXT: s_endpgm
665 ; GCN-IR-LABEL: s_test_urem23_64_v2i64:
666 ; GCN-IR: ; %bb.0:
667 ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
668 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
669 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
670 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
671 ; GCN-IR-NEXT: s_mov_b32 s2, -1
672 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
673 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1
674 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
675 ; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1
676 ; GCN-IR-NEXT: s_lshr_b32 s6, s7, 9
677 ; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9
678 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5
679 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0
680 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7
681 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6
682 ; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3
683 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4
684 ; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3
685 ; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2
686 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3
687 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
688 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6
689 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
690 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
691 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
692 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5
693 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
694 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
695 ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
696 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7
697 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
698 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
699 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
700 ; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
701 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
702 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
703 ; GCN-IR-NEXT: s_endpgm
816 ; GCN-IR-LABEL: s_test_urem_k_num_i64:
817 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
818 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
819 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
820 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
821 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
822 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
823 ; GCN-IR-NEXT: s_min_u32 s8, s4, s5
824 ; GCN-IR-NEXT: s_add_u32 s6, s8, 0xffffffc5
825 ; GCN-IR-NEXT: s_addc_u32 s7, 0, -1
826 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
827 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
828 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
829 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
830 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
831 ; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
832 ; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
833 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
834 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_5
835 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
836 ; GCN-IR-NEXT: s_add_u32 s10, s6, 1
837 ; GCN-IR-NEXT: s_addc_u32 s11, s7, 0
838 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
839 ; GCN-IR-NEXT: s_sub_i32 s6, 63, s6
840 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13]
841 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s6
842 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_4
843 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
844 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s10
845 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
846 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
847 ; GCN-IR-NEXT: s_sub_u32 s8, 58, s8
848 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
849 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
850 ; GCN-IR-NEXT: s_mov_b32 s5, 0
851 ; GCN-IR-NEXT: .LBB6_3: ; %udiv-do-while
852 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
853 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
854 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
855 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
856 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
857 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
858 ; GCN-IR-NEXT: s_sub_u32 s4, s14, s10
859 ; GCN-IR-NEXT: s_subb_u32 s4, s15, s11
860 ; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31
861 ; GCN-IR-NEXT: s_mov_b32 s13, s12
862 ; GCN-IR-NEXT: s_and_b32 s4, s12, 1
863 ; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], s[2:3]
864 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s12
865 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s13
866 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
867 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
868 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
869 ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5]
870 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
871 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_3
872 ; GCN-IR-NEXT: .LBB6_4: ; %Flow5
873 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
874 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
875 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
876 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
877 ; GCN-IR-NEXT: s_branch .LBB6_6
878 ; GCN-IR-NEXT: .LBB6_5:
879 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
880 ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11]
881 ; GCN-IR-NEXT: .LBB6_6: ; %udiv-end
882 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
883 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
884 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0
885 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0
886 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
887 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v2
888 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1
889 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
890 ; GCN-IR-NEXT: s_mov_b32 s6, -1
891 ; GCN-IR-NEXT: s_mov_b32 s4, s0
892 ; GCN-IR-NEXT: s_mov_b32 s5, s1
893 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
894 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
895 ; GCN-IR-NEXT: s_endpgm
1004 ; GCN-IR-LABEL: s_test_urem_k_den_i64:
1005 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1006 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1007 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1008 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
1009 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
1010 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
1011 ; GCN-IR-NEXT: s_min_u32 s8, s4, s5
1012 ; GCN-IR-NEXT: s_sub_u32 s6, 59, s8
1013 ; GCN-IR-NEXT: s_subb_u32 s7, 0, 0
1014 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1015 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1016 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
1017 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
1018 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1019 ; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
1020 ; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
1021 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
1022 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
1023 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1024 ; GCN-IR-NEXT: s_add_u32 s10, s6, 1
1025 ; GCN-IR-NEXT: s_addc_u32 s11, s7, 0
1026 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
1027 ; GCN-IR-NEXT: s_sub_i32 s6, 63, s6
1028 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13]
1029 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
1030 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
1031 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1032 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s10
1033 ; GCN-IR-NEXT: s_add_u32 s8, s8, 0xffffffc4
1034 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
1035 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
1036 ; GCN-IR-NEXT: s_mov_b32 s5, 0
1037 ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
1038 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1039 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
1040 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
1041 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
1042 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
1043 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
1044 ; GCN-IR-NEXT: s_sub_u32 s4, 23, s10
1045 ; GCN-IR-NEXT: s_subb_u32 s4, 0, s11
1046 ; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31
1047 ; GCN-IR-NEXT: s_and_b32 s4, s12, 1
1048 ; GCN-IR-NEXT: s_and_b32 s12, s12, 24
1049 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s12
1050 ; GCN-IR-NEXT: s_subb_u32 s11, s11, 0
1051 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
1052 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
1053 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 0
1054 ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5]
1055 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[14:15]
1056 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
1057 ; GCN-IR-NEXT: .LBB7_4: ; %Flow5
1058 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
1059 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
1060 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
1061 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
1062 ; GCN-IR-NEXT: s_branch .LBB7_6
1063 ; GCN-IR-NEXT: .LBB7_5:
1064 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
1065 ; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1066 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
1067 ; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1068 ; GCN-IR-NEXT: .LBB7_6: ; %udiv-end
1069 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, 24
1070 ; GCN-IR-NEXT: v_mul_hi_u32 v2, v0, 24
1071 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, 24
1072 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1073 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1074 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v2
1075 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
1076 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
1077 ; GCN-IR-NEXT: s_mov_b32 s4, s0
1078 ; GCN-IR-NEXT: s_mov_b32 s5, s1
1079 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
1080 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1081 ; GCN-IR-NEXT: s_endpgm
1187 ; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1188 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1189 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1190 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1191 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
1192 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1193 ; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
1194 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 0xffffffd0, v6
1195 ; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1196 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1197 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1198 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0x8000
1199 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1200 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1201 ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5]
1202 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
1203 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
1204 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000
1205 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
1206 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1207 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_6
1208 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1209 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v3
1210 ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v4, vcc
1211 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3
1212 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8]
1213 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
1214 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1215 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1216 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1217 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
1218 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_5
1219 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1220 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
1221 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
1222 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
1223 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v7
1224 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
1225 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
1226 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
1227 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1228 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
1229 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1230 ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
1231 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1232 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
1233 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1234 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
1235 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1236 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
1237 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
1238 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
1239 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
1240 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
1241 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
1242 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
1243 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
1244 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
1245 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
1246 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1247 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
1248 ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1249 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
1250 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1251 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
1252 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1253 ; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3
1254 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1255 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1256 ; GCN-IR-NEXT: .LBB8_5: ; %Flow3
1257 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1258 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1
1259 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7
1260 ; GCN-IR-NEXT: v_or_b32_e32 v5, v4, v6
1261 ; GCN-IR-NEXT: .LBB8_6: ; %Flow4
1262 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1263 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2
1264 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v5
1265 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v5
1266 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v5
1267 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
1268 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
1269 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
1270 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
1271 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1284 ; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1285 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1286 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1287 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1288 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
1289 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1290 ; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
1291 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 48, v6
1292 ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1293 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1294 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1295 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1296 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1297 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
1298 ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1299 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1300 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
1301 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1302 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
1303 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1304 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2
1305 ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
1306 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
1307 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8]
1308 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
1309 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1310 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1311 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1312 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
1313 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
1314 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1315 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7
1316 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6
1317 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
1318 ; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1319 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1320 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
1321 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1322 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
1323 ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
1324 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1325 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
1326 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1327 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
1328 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
1329 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1330 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
1331 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
1332 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
1333 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
1334 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
1335 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
1336 ; GCN-IR-NEXT: v_and_b32_e32 v10, 0x8000, v10
1337 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1338 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
1339 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
1340 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
1341 ; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
1342 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1343 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
1344 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1345 ; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
1346 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1347 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1348 ; GCN-IR-NEXT: .LBB9_5: ; %Flow3
1349 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1350 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1351 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
1352 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
1353 ; GCN-IR-NEXT: .LBB9_6: ; %Flow4
1354 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1355 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15
1356 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1357 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
1358 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1387 ; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1388 ; GCN-IR: ; %bb.0:
1389 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1390 ; GCN-IR-NEXT: s_mov_b32 s5, 0x41c00000
1391 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1392 ; GCN-IR-NEXT: s_mov_b32 s2, -1
1393 ; GCN-IR-NEXT: s_lshr_b32 s4, s3, 8
1394 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
1395 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
1396 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
1397 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1398 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1399 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1400 ; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s5
1401 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1402 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1403 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1404 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
1405 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1406 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1407 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1408 ; GCN-IR-NEXT: s_endpgm
1441 ; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1442 ; GCN-IR: ; %bb.0:
1443 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1444 ; GCN-IR-NEXT: s_movk_i32 s4, 0x5b7f
1445 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1446 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1447 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1448 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
1449 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
1450 ; GCN-IR-NEXT: s_mov_b32 s3, 0x46b6fe00
1451 ; GCN-IR-NEXT: s_mov_b32 s5, s1
1452 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
1453 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1454 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1455 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s3, v0
1456 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s3
1457 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1458 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1459 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
1460 ; GCN-IR-NEXT: s_mov_b32 s4, s0
1461 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
1462 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1463 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1464 ; GCN-IR-NEXT: s_endpgm
1491 ; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1492 ; GCN-IR: ; %bb.0:
1493 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1494 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1495 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
1496 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
1497 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
1498 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
1499 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1500 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
1501 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
1502 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
1503 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1504 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
1505 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1506 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1507 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1508 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1534 ; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1535 ; GCN-IR: ; %bb.0:
1536 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1537 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1538 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
1539 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1540 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
1541 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
1542 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1543 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
1544 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
1545 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
1546 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1547 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
1548 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1549 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
1550 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1551 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1565 ; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1566 ; GCN-IR: ; %bb.0:
1567 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1568 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1569 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
1570 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1571 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v1
1572 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1573 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
1574 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, s4, v1
1575 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4
1576 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1577 ; GCN-IR-NEXT: v_lshlrev_b32_e32 v1, 15, v1
1578 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
1579 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1580 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1581 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]