Lines Matching refs:IR
3 …t -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s
49 ; IR-LABEL: @reduced_nested_loop_conditions(
50 ; IR-NEXT: bb:
51 ; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4
52 ; IR-NEXT: [[MY_TMP1:%.*]] = getelementptr inbounds i64, i64 addrspace(3)* [[ARG:%.*]], i32 [[MY…
53 ; IR-NEXT: [[MY_TMP2:%.*]] = load volatile i64, i64 addrspace(3)* [[MY_TMP1]]
54 ; IR-NEXT: br label [[BB5:%.*]]
55 ; IR: bb3:
56 ; IR-NEXT: br i1 true, label [[BB4:%.*]], label [[BB13:%.*]]
57 ; IR: bb4:
58 ; IR-NEXT: br label [[FLOW:%.*]]
59 ; IR: bb5:
60 ; IR-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP6:%.*]], [[BB10:%.*]] ], [ 0, [[BB:%.*]] ]
61 ; IR-NEXT: [[MY_TMP6:%.*]] = phi i32 [ 0, [[BB]] ], [ [[TMP5:%.*]], [[BB10]] ]
62 ; IR-NEXT: [[MY_TMP7:%.*]] = icmp eq i32 [[MY_TMP6]], 1
63 ; IR-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[MY_TMP7]])
64 ; IR-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
65 ; IR-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1
66 ; IR-NEXT: br i1 [[TMP1]], label [[BB8:%.*]], label [[FLOW]]
67 ; IR: bb8:
68 ; IR-NEXT: br label [[BB13]]
69 ; IR: bb9:
70 ; IR-NEXT: br i1 false, label [[BB3:%.*]], label [[BB9:%.*]]
71 ; IR: bb10:
72 ; IR-NEXT: [[TMP3:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP6]])
73 ; IR-NEXT: br i1 [[TMP3]], label [[BB23:%.*]], label [[BB5]]
74 ; IR: Flow:
75 ; IR-NEXT: [[TMP4:%.*]] = phi i1 [ [[MY_TMP22:%.*]], [[BB4]] ], [ true, [[BB5]] ]
76 ; IR-NEXT: [[TMP5]] = phi i32 [ [[MY_TMP21:%.*]], [[BB4]] ], [ undef, [[BB5]] ]
77 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
78 ; IR-NEXT: [[TMP6]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]])
79 ; IR-NEXT: br label [[BB10]]
80 ; IR: bb13:
81 ; IR-NEXT: [[MY_TMP14:%.*]] = phi i1 [ [[MY_TMP22]], [[BB3]] ], [ true, [[BB8]] ]
82 ; IR-NEXT: [[MY_TMP15:%.*]] = bitcast i64 [[MY_TMP2]] to <2 x i32>
83 ; IR-NEXT: br i1 [[MY_TMP14]], label [[BB16:%.*]], label [[BB20:%.*]]
84 ; IR: bb16:
85 ; IR-NEXT: [[MY_TMP17:%.*]] = extractelement <2 x i32> [[MY_TMP15]], i64 1
86 ; IR-NEXT: [[MY_TMP18:%.*]] = getelementptr inbounds i32, i32 addrspace(3)* undef, i32 [[MY_TMP1…
87 ; IR-NEXT: [[MY_TMP19:%.*]] = load volatile i32, i32 addrspace(3)* [[MY_TMP18]]
88 ; IR-NEXT: br label [[BB20]]
89 ; IR: bb20:
90 ; IR-NEXT: [[MY_TMP21]] = phi i32 [ [[MY_TMP19]], [[BB16]] ], [ 0, [[BB13]] ]
91 ; IR-NEXT: [[MY_TMP22]] = phi i1 [ false, [[BB16]] ], [ [[MY_TMP14]], [[BB13]] ]
92 ; IR-NEXT: br label [[BB9]]
93 ; IR: bb23:
94 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP6]])
95 ; IR-NEXT: ret void
191 ; IR-LABEL: @nested_loop_conditions(
192 ; IR-NEXT: bb:
193 ; IR-NEXT: [[MY_TMP1134:%.*]] = load volatile i32, i32 addrspace(1)* undef
194 ; IR-NEXT: [[MY_TMP1235:%.*]] = icmp slt i32 [[MY_TMP1134]], 9
195 ; IR-NEXT: br i1 [[MY_TMP1235]], label [[BB14_LR_PH:%.*]], label [[FLOW:%.*]]
196 ; IR: bb14.lr.ph:
197 ; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4
198 ; IR-NEXT: [[MY_TMP1:%.*]] = zext i32 [[MY_TMP]] to i64
199 ; IR-NEXT: [[MY_TMP2:%.*]] = getelementptr inbounds i64, i64 addrspace(1)* [[ARG:%.*]], i64 [[MY…
200 ; IR-NEXT: [[MY_TMP3:%.*]] = load i64, i64 addrspace(1)* [[MY_TMP2]], align 16
201 ; IR-NEXT: [[MY_TMP932:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* undef, align 16
202 ; IR-NEXT: [[MY_TMP1033:%.*]] = extractelement <4 x i32> [[MY_TMP932]], i64 0
203 ; IR-NEXT: br label [[BB14:%.*]]
204 ; IR: Flow3:
205 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP21:%.*]])
206 ; IR-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP14:%.*]])
207 ; IR-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
208 ; IR-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1
209 ; IR-NEXT: br i1 [[TMP1]], label [[BB4_BB13_CRIT_EDGE:%.*]], label [[FLOW4:%.*]]
210 ; IR: bb4.bb13_crit_edge:
211 ; IR-NEXT: br label [[FLOW4]]
212 ; IR: Flow4:
213 ; IR-NEXT: [[TMP3:%.*]] = phi i1 [ true, [[BB4_BB13_CRIT_EDGE]] ], [ false, [[FLOW3:%.*]] ]
214 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
215 ; IR-NEXT: br label [[FLOW]]
216 ; IR: bb13:
217 ; IR-NEXT: br label [[BB31:%.*]]
218 ; IR: Flow:
219 ; IR-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP3]], [[FLOW4]] ], [ true, [[BB:%.*]] ]
220 ; IR-NEXT: [[TMP5:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP4]])
221 ; IR-NEXT: [[TMP6:%.*]] = extractvalue { i1, i64 } [[TMP5]], 0
222 ; IR-NEXT: [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP5]], 1
223 ; IR-NEXT: br i1 [[TMP6]], label [[BB13:%.*]], label [[BB31]]
224 ; IR: bb14:
225 ; IR-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP16:%.*]], [[FLOW1:%.*]] ], [ 0, [[BB14_LR_PH]] ]
226 ; IR-NEXT: [[MY_TMP1037:%.*]] = phi i32 [ [[MY_TMP1033]], [[BB14_LR_PH]] ], [ [[TMP12:%.*]], [[F…
227 ; IR-NEXT: [[MY_TMP936:%.*]] = phi <4 x i32> [ [[MY_TMP932]], [[BB14_LR_PH]] ], [ [[TMP11:%.*]],…
228 ; IR-NEXT: [[MY_TMP15:%.*]] = icmp eq i32 [[MY_TMP1037]], 1
229 ; IR-NEXT: [[TMP8:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[MY_TMP15]])
230 ; IR-NEXT: [[TMP9:%.*]] = extractvalue { i1, i64 } [[TMP8]], 0
231 ; IR-NEXT: [[TMP10:%.*]] = extractvalue { i1, i64 } [[TMP8]], 1
232 ; IR-NEXT: br i1 [[TMP9]], label [[BB16:%.*]], label [[FLOW1]]
233 ; IR: bb16:
234 ; IR-NEXT: [[MY_TMP17:%.*]] = bitcast i64 [[MY_TMP3]] to <2 x i32>
235 ; IR-NEXT: br label [[BB18:%.*]]
236 ; IR: Flow1:
237 ; IR-NEXT: [[TMP11]] = phi <4 x i32> [ [[MY_TMP9:%.*]], [[BB21:%.*]] ], [ undef, [[BB14]] ]
238 ; IR-NEXT: [[TMP12]] = phi i32 [ [[MY_TMP10:%.*]], [[BB21]] ], [ undef, [[BB14]] ]
239 ; IR-NEXT: [[TMP13:%.*]] = phi i1 [ [[MY_TMP12:%.*]], [[BB21]] ], [ true, [[BB14]] ]
240 ; IR-NEXT: [[TMP14]] = phi i1 [ [[MY_TMP12]], [[BB21]] ], [ false, [[BB14]] ]
241 ; IR-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[BB21]] ], [ true, [[BB14]] ]
242 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP10]])
243 ; IR-NEXT: [[TMP16]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP13]], i64 [[PHI_BROKEN]])
244 ; IR-NEXT: [[TMP17:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP16]])
245 ; IR-NEXT: br i1 [[TMP17]], label [[FLOW2:%.*]], label [[BB14]]
246 ; IR: bb18:
247 ; IR-NEXT: [[MY_TMP19:%.*]] = load volatile i32, i32 addrspace(1)* undef
248 ; IR-NEXT: [[MY_TMP20:%.*]] = icmp slt i32 [[MY_TMP19]], 9
249 ; IR-NEXT: br i1 [[MY_TMP20]], label [[BB21]], label [[BB18]]
250 ; IR: bb21:
251 ; IR-NEXT: [[MY_TMP22:%.*]] = extractelement <2 x i32> [[MY_TMP17]], i64 1
252 ; IR-NEXT: [[MY_TMP23:%.*]] = lshr i32 [[MY_TMP22]], 16
253 ; IR-NEXT: [[MY_TMP24:%.*]] = select i1 undef, i32 undef, i32 [[MY_TMP23]]
254 ; IR-NEXT: [[MY_TMP25:%.*]] = uitofp i32 [[MY_TMP24]] to float
255 ; IR-NEXT: [[MY_TMP26:%.*]] = fmul float [[MY_TMP25]], 0x3EF0001000000000
256 ; IR-NEXT: [[MY_TMP27:%.*]] = fsub float [[MY_TMP26]], undef
257 ; IR-NEXT: [[MY_TMP28:%.*]] = fcmp olt float [[MY_TMP27]], 5.000000e-01
258 ; IR-NEXT: [[MY_TMP29:%.*]] = select i1 [[MY_TMP28]], i64 1, i64 2
259 ; IR-NEXT: [[MY_TMP30:%.*]] = extractelement <4 x i32> [[MY_TMP936]], i64 [[MY_TMP29]]
260 ; IR-NEXT: [[MY_TMP7:%.*]] = zext i32 [[MY_TMP30]] to i64
261 ; IR-NEXT: [[MY_TMP8:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i6…
262 ; IR-NEXT: [[MY_TMP9]] = load <4 x i32>, <4 x i32> addrspace(1)* [[MY_TMP8]], align 16
263 ; IR-NEXT: [[MY_TMP10]] = extractelement <4 x i32> [[MY_TMP9]], i64 0
264 ; IR-NEXT: [[MY_TMP11:%.*]] = load volatile i32, i32 addrspace(1)* undef
265 ; IR-NEXT: [[MY_TMP12]] = icmp sge i32 [[MY_TMP11]], 9
266 ; IR-NEXT: br label [[FLOW1]]
267 ; IR: Flow2:
268 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP16]])
269 ; IR-NEXT: [[TMP19:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP15]])
270 ; IR-NEXT: [[TMP20:%.*]] = extractvalue { i1, i64 } [[TMP19]], 0
271 ; IR-NEXT: [[TMP21]] = extractvalue { i1, i64 } [[TMP19]], 1
272 ; IR-NEXT: br i1 [[TMP20]], label [[BB31_LOOPEXIT:%.*]], label [[FLOW3]]
273 ; IR: bb31.loopexit:
274 ; IR-NEXT: br label [[FLOW3]]
275 ; IR: bb31:
276 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP7]])
277 ; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef
278 ; IR-NEXT: ret void