Lines Matching refs:IR
2 … -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=IR %s
6 ; IR-LABEL: @select_sdiv_lhs_const_i32(
7 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 200000, i32 125000
8 ; IR-NEXT: ret i32 [[OP]]
25 ; IR-LABEL: @select_sdiv_rhs_const_i32(
26 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000, i32 10000
27 ; IR-NEXT: ret i32 [[OP]]
44 ; IR-LABEL: @select_sdiv_lhs_const_v2i32(
45 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 666, i32 poison>, <2 x i32> <i32 …
46 ; IR-NEXT: ret <2 x i32> [[OP]]
64 ; IR-LABEL: @select_sdiv_rhs_const_v2i32(
65 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], <2 x i32> <i32 198621, i32 20855308>, <2 x i32> …
66 ; IR-NEXT: ret <2 x i32> [[OP]]
88 ; IR-LABEL: @select_sdiv_lhs_opaque_const0_i32(
89 ; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (i32 addrspace(1)* @gv to i32),…
90 ; IR-NEXT: [[TMP1:%.*]] = ashr i32 [[SELECT]], 31
91 ; IR-NEXT: [[TMP2:%.*]] = xor i32 0, [[TMP1]]
92 ; IR-NEXT: [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]
93 ; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
94 ; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
95 ; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])
96 ; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41EFFFFFC0000000
97 ; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
98 ; IR-NEXT: [[TMP9:%.*]] = sub i32 0, [[TMP4]]
99 ; IR-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP8]]
100 ; IR-NEXT: [[TMP11:%.*]] = zext i32 [[TMP8]] to i64
101 ; IR-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64
102 ; IR-NEXT: [[TMP13:%.*]] = mul i64 [[TMP11]], [[TMP12]]
103 ; IR-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
104 ; IR-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 32
105 ; IR-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
106 ; IR-NEXT: [[TMP17:%.*]] = add i32 [[TMP8]], [[TMP16]]
107 ; IR-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
108 ; IR-NEXT: [[TMP19:%.*]] = mul i64 1000000, [[TMP18]]
109 ; IR-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
110 ; IR-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP19]], 32
111 ; IR-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
112 ; IR-NEXT: [[TMP23:%.*]] = mul i32 [[TMP22]], [[TMP4]]
113 ; IR-NEXT: [[TMP24:%.*]] = sub i32 1000000, [[TMP23]]
114 ; IR-NEXT: [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[TMP4]]
115 ; IR-NEXT: [[TMP26:%.*]] = add i32 [[TMP22]], 1
116 ; IR-NEXT: [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP22]]
117 ; IR-NEXT: [[TMP28:%.*]] = sub i32 [[TMP24]], [[TMP4]]
118 ; IR-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i32 [[TMP28]], i32 [[TMP24]]
119 ; IR-NEXT: [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP4]]
120 ; IR-NEXT: [[TMP31:%.*]] = add i32 [[TMP27]], 1
121 ; IR-NEXT: [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP27]]
122 ; IR-NEXT: [[TMP33:%.*]] = xor i32 [[TMP32]], [[TMP2]]
123 ; IR-NEXT: [[TMP34:%.*]] = sub i32 [[TMP33]], [[TMP2]]
124 ; IR-NEXT: ret i32 [[TMP34]]
170 ; IR-LABEL: @select_sdiv_lhs_opaque_const1_i32(
171 ; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 5, i32 ptrtoint (i32 addrspace(1)* @gv t…
172 ; IR-NEXT: [[TMP1:%.*]] = ashr i32 [[SELECT]], 31
173 ; IR-NEXT: [[TMP2:%.*]] = xor i32 0, [[TMP1]]
174 ; IR-NEXT: [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]]
175 ; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]]
176 ; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
177 ; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]])
178 ; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41EFFFFFC0000000
179 ; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i32
180 ; IR-NEXT: [[TMP9:%.*]] = sub i32 0, [[TMP4]]
181 ; IR-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP8]]
182 ; IR-NEXT: [[TMP11:%.*]] = zext i32 [[TMP8]] to i64
183 ; IR-NEXT: [[TMP12:%.*]] = zext i32 [[TMP10]] to i64
184 ; IR-NEXT: [[TMP13:%.*]] = mul i64 [[TMP11]], [[TMP12]]
185 ; IR-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
186 ; IR-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 32
187 ; IR-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
188 ; IR-NEXT: [[TMP17:%.*]] = add i32 [[TMP8]], [[TMP16]]
189 ; IR-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
190 ; IR-NEXT: [[TMP19:%.*]] = mul i64 1000000, [[TMP18]]
191 ; IR-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
192 ; IR-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP19]], 32
193 ; IR-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
194 ; IR-NEXT: [[TMP23:%.*]] = mul i32 [[TMP22]], [[TMP4]]
195 ; IR-NEXT: [[TMP24:%.*]] = sub i32 1000000, [[TMP23]]
196 ; IR-NEXT: [[TMP25:%.*]] = icmp uge i32 [[TMP24]], [[TMP4]]
197 ; IR-NEXT: [[TMP26:%.*]] = add i32 [[TMP22]], 1
198 ; IR-NEXT: [[TMP27:%.*]] = select i1 [[TMP25]], i32 [[TMP26]], i32 [[TMP22]]
199 ; IR-NEXT: [[TMP28:%.*]] = sub i32 [[TMP24]], [[TMP4]]
200 ; IR-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i32 [[TMP28]], i32 [[TMP24]]
201 ; IR-NEXT: [[TMP30:%.*]] = icmp uge i32 [[TMP29]], [[TMP4]]
202 ; IR-NEXT: [[TMP31:%.*]] = add i32 [[TMP27]], 1
203 ; IR-NEXT: [[TMP32:%.*]] = select i1 [[TMP30]], i32 [[TMP31]], i32 [[TMP27]]
204 ; IR-NEXT: [[TMP33:%.*]] = xor i32 [[TMP32]], [[TMP2]]
205 ; IR-NEXT: [[TMP34:%.*]] = sub i32 [[TMP33]], [[TMP2]]
206 ; IR-NEXT: ret i32 [[TMP34]]
252 ; IR-LABEL: @select_sdiv_rhs_opaque_const0_i32(
253 ; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 ptrtoint (i32 addrspace(1)* @gv to i32),…
254 ; IR-NEXT: [[OP:%.*]] = sdiv i32 [[SELECT]], 42
255 ; IR-NEXT: ret i32 [[OP]]
282 ; IR-LABEL: @select_sdiv_rhs_opaque_const1_i32(
283 ; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], i32 42000, i32 ptrtoint (i32 addrspace(1)* @…
284 ; IR-NEXT: [[OP:%.*]] = sdiv i32 [[SELECT]], 42
285 ; IR-NEXT: ret i32 [[OP]]
312 ; IR-LABEL: @select_add_lhs_const_i32(
313 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 1000005, i32 1000008
314 ; IR-NEXT: ret i32 [[OP]]
331 ; IR-LABEL: @select_fadd_lhs_const_i32_fmf(
332 ; IR-NEXT: [[OP:%.*]] = select nnan nsz i1 [[COND:%.*]], float 3.000000e+00, float 5.000000e+00
333 ; IR-NEXT: ret float [[OP]]
360 ; IR-LABEL: @select_mul_lhs_const_i32(
361 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000
362 ; IR-NEXT: ret i32 [[OP]]
379 ; IR-LABEL: @select_mul_rhs_const_i32(
380 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 5000, i32 8000
381 ; IR-NEXT: ret i32 [[OP]]
388 ; IR-LABEL: @select_add_lhs_const_i16(
389 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i16 128, i16 131
390 ; IR-NEXT: store i16 [[OP]], i16 addrspace(1)* undef, align 2
391 ; IR-NEXT: ret void
418 ; IR-LABEL: @select_add_trunc_select(
419 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i16 47, i16 50
420 ; IR-NEXT: ret i16 [[OP]]
428 ; IR-LABEL: @select_add_sext_select(
429 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 29, i32 50
430 ; IR-NEXT: ret i32 [[OP]]
446 ; IR-LABEL: @select_add_zext_select(
447 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 47, i32 50
448 ; IR-NEXT: ret i32 [[OP]]
464 ; IR-LABEL: @select_add_bitcast_select(
465 ; IR-NEXT: [[OP:%.*]] = select i1 [[COND:%.*]], i32 1065353258, i32 1073741866
466 ; IR-NEXT: ret i32 [[OP]]
486 ; IR-LABEL: @multi_use_cast_regression(
487 ; IR-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], half 0xH3C00, half 0xH0000
488 ; IR-NEXT: [[FPEXT:%.*]] = fpext half [[SELECT]] to float
489 ; IR-NEXT: [[FSUB:%.*]] = fsub nsz float 1.000000e+00, [[FPEXT]]
490 ; IR-NEXT: [[CALL:%.*]] = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[FPEXT]], float [[FS…
491 ; IR-NEXT: ret <2 x half> [[CALL]]