Lines Matching refs:IR
1 …nnotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
2 …nnotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
5 ; Add an extra verifier runs. There were some cases where invalid IR
12 ; IR-LABEL: @multi_divergent_region_exit_ret_ret(
13 ; IR: %0 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %Pivot)
14 ; IR: %1 = extractvalue { i1, i64 } %0, 0
15 ; IR: %2 = extractvalue { i1, i64 } %0, 1
16 ; IR: br i1 %1, label %LeafBlock1, label %Flow
18 ; IR: Flow:
19 ; IR: %3 = phi i1 [ true, %LeafBlock1 ], [ false, %entry ]
20 ; IR: %4 = phi i1 [ %SwitchLeaf2, %LeafBlock1 ], [ false, %entry ]
21 ; IR: %5 = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %2)
22 ; IR: %6 = extractvalue { i1, i64 } %5, 0
23 ; IR: %7 = extractvalue { i1, i64 } %5, 1
24 ; IR: br i1 %6, label %LeafBlock, label %Flow1
26 ; IR: LeafBlock:
27 ; IR: br label %Flow1
29 ; IR: LeafBlock1:
30 ; IR: br label %Flow{{$}}
32 ; IR: Flow2:
33 ; IR: %8 = phi i1 [ false, %exit1 ], [ %12, %Flow1 ]
34 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %16)
35 ; IR: %9 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %8)
36 ; IR: %10 = extractvalue { i1, i64 } %9, 0
37 ; IR: %11 = extractvalue { i1, i64 } %9, 1
38 ; IR: br i1 %10, label %exit0, label %UnifiedReturnBlock
40 ; IR: exit0:
41 ; IR: store volatile i32 9, i32 addrspace(1)* undef
42 ; IR: br label %UnifiedReturnBlock
44 ; IR: Flow1:
45 ; IR: %12 = phi i1 [ %SwitchLeaf, %LeafBlock ], [ %3, %Flow ]
46 ; IR: %13 = phi i1 [ %SwitchLeaf.inv, %LeafBlock ], [ %4, %Flow ]
47 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %7)
48 ; IR: %14 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %13)
49 ; IR: %15 = extractvalue { i1, i64 } %14, 0
50 ; IR: %16 = extractvalue { i1, i64 } %14, 1
51 ; IR: br i1 %15, label %exit1, label %Flow2
53 ; IR: exit1:
54 ; IR: store volatile i32 17, i32 addrspace(3)* undef
55 ; IR: br label %Flow2
57 ; IR: UnifiedReturnBlock:
58 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %11)
59 ; IR: ret void
142 ; IR-LABEL: @multi_divergent_region_exit_unreachable_unreachable(
143 ; IR: %0 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %Pivot)
145 ; IR: %5 = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %2)
147 ; IR: %8 = phi i1 [ false, %exit1 ], [ %12, %Flow1 ]
148 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %16)
149 ; IR: %9 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %8)
150 ; IR: br i1 %10, label %exit0, label %UnifiedUnreachableBlock
153 ; IR: UnifiedUnreachableBlock:
154 ; IR-NEXT: unreachable
197 ; IR-LABEL: @multi_exit_region_divergent_ret_uniform_ret(
198 ; IR: %divergent.cond0 = icmp sge i32 %tmp16, 2
199 ; IR: llvm.amdgcn.if
200 ; IR: br i1
202 ; IR: {{^}}Flow:
203 ; IR: %3 = phi i1 [ true, %LeafBlock1 ], [ false, %entry ]
204 ; IR: %4 = phi i1 [ %uniform.cond0, %LeafBlock1 ], [ false, %entry ]
205 ; IR: %5 = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %2)
206 ; IR: br i1 %6, label %LeafBlock, label %Flow1
208 ; IR: {{^}}LeafBlock:
209 ; IR: %divergent.cond1 = icmp eq i32 %tmp16, 1
210 ; IR: br label %Flow1
212 ; IR: LeafBlock1:
213 ; IR: %uniform.cond0 = icmp ne i32 %arg3, 2
214 ; IR: br label %Flow
216 ; IR: Flow2:
217 ; IR: %8 = phi i1 [ false, %exit1 ], [ %12, %Flow1 ]
218 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %16)
219 ; IR: %9 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %8)
220 ; IR: br i1 %10, label %exit0, label %UnifiedReturnBlock
222 ; IR: exit0:
223 ; IR: store volatile i32 9, i32 addrspace(1)* undef
224 ; IR: br label %UnifiedReturnBlock
226 ; IR: {{^}}Flow1:
227 ; IR: %12 = phi i1 [ %divergent.cond1, %LeafBlock ], [ %3, %Flow ]
228 ; IR: %13 = phi i1 [ %divergent.cond1.inv, %LeafBlock ], [ %4, %Flow ]
229 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %7)
230 ; IR: %14 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %13)
231 ; IR: %15 = extractvalue { i1, i64 } %14, 0
232 ; IR: %16 = extractvalue { i1, i64 } %14, 1
233 ; IR: br i1 %15, label %exit1, label %Flow2
235 ; IR: exit1:
236 ; IR: store volatile i32 17, i32 addrspace(3)* undef
237 ; IR: br label %Flow2
239 ; IR: UnifiedReturnBlock:
240 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %11)
241 ; IR: ret void
278 ; IR-LABEL: @multi_exit_region_uniform_ret_divergent_ret(
279 ; IR: %0 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %Pivot)
280 ; IR: br i1 %1, label %LeafBlock1, label %Flow
282 ; IR: Flow:
283 ; IR: %3 = phi i1 [ true, %LeafBlock1 ], [ false, %entry ]
284 ; IR: %4 = phi i1 [ %SwitchLeaf2, %LeafBlock1 ], [ false, %entry ]
285 ; IR: %5 = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %2)
287 ; IR: %8 = phi i1 [ false, %exit1 ], [ %12, %Flow1 ]
288 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %16)
289 ; IR: %9 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %8)
327 ; IR-LABEL: @multi_divergent_region_exit_ret_ret_return_value(
328 ; IR: Flow2:
329 ; IR: %8 = phi i1 [ false, %exit1 ], [ %12, %Flow1 ]
330 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %16)
332 ; IR: UnifiedReturnBlock:
333 ; IR: %UnifiedRetVal = phi float [ 2.000000e+00, %Flow2 ], [ 1.000000e+00, %exit0 ]
334 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %11)
335 ; IR: ret float %UnifiedRetVal
358 ; IR-LABEL: @uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value(
400 ; IR-LABEL: @multi_divergent_region_exit_ret_unreachable(
401 ; IR: %0 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %Pivot)
403 ; IR: Flow:
404 ; IR: %3 = phi i1 [ true, %LeafBlock1 ], [ false, %entry ]
405 ; IR: %4 = phi i1 [ %SwitchLeaf2, %LeafBlock1 ], [ false, %entry ]
406 ; IR: %5 = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %2)
408 ; IR: Flow2:
409 ; IR: %8 = phi i1 [ false, %exit1 ], [ %12, %Flow1 ]
410 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %16)
411 ; IR: %9 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %8)
412 ; IR: br i1 %10, label %exit0, label %UnifiedReturnBlock
414 ; IR: exit0:
415 ; IR-NEXT: store volatile i32 17, i32 addrspace(3)* undef
416 ; IR-NEXT: br label %UnifiedReturnBlock
418 ; IR: Flow1:
419 ; IR: %12 = phi i1 [ %SwitchLeaf, %LeafBlock ], [ %3, %Flow ]
420 ; IR: %13 = phi i1 [ %SwitchLeaf.inv, %LeafBlock ], [ %4, %Flow ]
421 ; IR: call void @llvm.amdgcn.end.cf.i64(i64 %7)
422 ; IR: %14 = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %13)
423 ; IR: %15 = extractvalue { i1, i64 } %14, 0
424 ; IR: %16 = extractvalue { i1, i64 } %14, 1
425 ; IR: br i1 %15, label %exit1, label %Flow2
427 ; IR: exit1:
428 ; IR-NEXT: store volatile i32 9, i32 addrspace(1)* undef
429 ; IR-NEXT: call void @llvm.amdgcn.unreachable()
430 ; IR-NEXT: br label %Flow2
432 ; IR: UnifiedReturnBlock:
433 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %11)
434 ; IR-NEXT: ret void
474 ; IR-LABEL: @indirect_multi_divergent_region_exit_ret_unreachable(
476 ; IR: exit0: ; preds = %Flow2
477 ; IR-NEXT: store volatile i32 17, i32 addrspace(3)* undef
478 ; IR-NEXT: br label %UnifiedReturnBlock
481 ; IR: indirect.exit1:
482 ; IR: %load = load volatile i32, i32 addrspace(1)* undef
483 ; IR: store volatile i32 %load, i32 addrspace(1)* undef
484 ; IR: store volatile i32 9, i32 addrspace(1)* undef
485 ; IR: call void @llvm.amdgcn.unreachable()
486 ; IR-NEXT: br label %Flow2
488 ; IR: UnifiedReturnBlock: ; preds = %exit0, %Flow2
489 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %11)
490 ; IR-NEXT: ret void
532 ; IR-LABEL: @multi_divergent_region_exit_ret_switch(
571 ; IR-LABEL: @divergent_multi_ret_nest_in_uniform_triangle(
595 ; IR-LABEL: @divergent_complex_multi_ret_nest_in_uniform_triangle(
634 ; IR-LABEL: @uniform_complex_multi_ret_nest_in_divergent_triangle(
635 ; IR: Flow1: ; preds = %uniform.ret1, %uniform.multi.exi…
636 ; IR: %6 = phi i1 [ false, %uniform.ret1 ], [ true, %uniform.multi.exit.region ]
637 ; IR: br i1 %6, label %uniform.if, label %Flow2
639 ; IR: Flow: ; preds = %uniform.then, %uniform.if
640 ; IR: %7 = phi i1 [ %uniform.cond2, %uniform.then ], [ %uniform.cond1.inv, %uniform.if ]
641 ; IR: br i1 %7, label %uniform.endif, label %uniform.ret0
643 ; IR: UnifiedReturnBlock: ; preds = %Flow3, %Flow2
644 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %5)
645 ; IR-NEXT: ret void
684 ; IR-LABEL: @multi_divergent_unreachable_exit(
685 ; IR: UnifiedUnreachableBlock:
686 ; IR-NEXT: call void @llvm.amdgcn.unreachable()
687 ; IR-NEXT: br label %UnifiedReturnBlock
689 ; IR: UnifiedReturnBlock:
690 ; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64
691 ; IR-NEXT: ret void
722 ; IR-LABEL: @uniformly_reached_export
723 ; IR-NEXT: .entry:
724 ; IR: br i1 [[CND:%.*]], label %[[LOOP:.*]], label %[[EXP:.*]]
726 ; IR: [[LOOP]]:
727 ; IR-NEXT: br i1 false, label %DummyReturnBlock, label %[[LOOP]]
729 ; IR: [[EXP]]:
730 ; IR-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> <half 0xH…
731 ; IR-NEXT: ret void
733 ; IR: DummyReturnBlock:
734 ; IR-NEXT: ret void