40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {  in isAvailable()  argument
42       Resources->canBeDispatched(IR.getInstruction()->getUsedBuffers());  in isAvailable()
55   LSUnit::Status LSS = LSU.isAvailable(IR);  in isAvailable()
71     InstRef &IR,  in issueInstructionImpl()  argument
73   Instruction *IS = IR.getInstruction();  in issueInstructionImpl()
82   IS->execute(IR.getSourceIndex());  in issueInstructionImpl()
87     LSU.onInstructionIssued(IR);  in issueInstructionImpl()
93     IssuedSet.emplace_back(IR);  in issueInstructionImpl()
95     LSU.onInstructionExecuted(IR);  in issueInstructionImpl()
100     InstRef &IR,  in issueInstruction()  argument
104   const Instruction &Inst = *IR.getInstruction();  in issueInstruction()
106   HasDependentUsers |= Inst.isMemOp() && LSU.hasDependentUsers(IR);  in issueInstruction()
109   issueInstructionImpl(IR, UsedResources);  in issueInstruction()
124     InstRef &IR = *I;  in promoteToReadySet()  local
125     if (!IR)  in promoteToReadySet()
129     Instruction &IS = *IR.getInstruction();  in promoteToReadySet()
135     if (IS.isMemOp() && !LSU.isReady(IR)) {  in promoteToReadySet()
140     LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR  in promoteToReadySet()
143     Ready.emplace_back(IR);  in promoteToReadySet()
144     ReadySet.emplace_back(IR);  in promoteToReadySet()
146     IR.invalidate();  in promoteToReadySet()
160     InstRef &IR = *I;  in promoteToPendingSet()  local
161     if (!IR)  in promoteToPendingSet()
166     Instruction &IS = *IR.getInstruction();  in promoteToPendingSet()
172     if (IS.isMemOp() && LSU.isWaiting(IR)) {  in promoteToPendingSet()
177     LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR  in promoteToPendingSet()
180     Pending.emplace_back(IR);  in promoteToPendingSet()
181     PendingSet.emplace_back(IR);  in promoteToPendingSet()
183     IR.invalidate();  in promoteToPendingSet()
195     InstRef &IR = ReadySet[I];  in select()  local
197         Strategy->compare(IR, ReadySet[QueueIndex])) {  in select()
198       Instruction &IS = *IR.getInstruction();  in select()
212   InstRef IR = ReadySet[QueueIndex];  in select()  local
215   return IR;  in select()
221     InstRef &IR = *I;  in updateIssuedSet()  local
222     if (!IR)  in updateIssuedSet()
224     Instruction &IS = *IR.getInstruction();  in updateIssuedSet()
226       LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR  in updateIssuedSet()
233     LSU.onInstructionExecuted(IR);  in updateIssuedSet()
234     Executed.emplace_back(IR);  in updateIssuedSet()
236     IR.invalidate();  in updateIssuedSet()
251   for (const InstRef &IR : make_range(PendingSet.begin(), EndIt)) {  in analyzeDataDependencies()  local
252     const Instruction &IS = *IR.getInstruction();  in analyzeDataDependencies()
256     if (IS.isMemOp() && LSU.isPending(IR))  in analyzeDataDependencies()
257       MemDeps.emplace_back(IR);  in analyzeDataDependencies()
260       RegDeps.emplace_back(IR);  in analyzeDataDependencies()
273   for (InstRef &IR : IssuedSet)  in cycleEvent()
274     IR.getInstruction()->cycleEvent();  in cycleEvent()
277   for (InstRef &IR : PendingSet)  in cycleEvent()
278     IR.getInstruction()->cycleEvent();  in cycleEvent()
280   for (InstRef &IR : WaitSet)  in cycleEvent()
281     IR.getInstruction()->cycleEvent();  in cycleEvent()
290 bool Scheduler::mustIssueImmediately(const InstRef &IR) const {  in mustIssueImmediately()
291   const InstrDesc &Desc = IR.getInstruction()->getDesc();  in mustIssueImmediately()
300 bool Scheduler::dispatch(InstRef &IR) {  in dispatch()  argument
301   Instruction &IS = *IR.getInstruction();  in dispatch()
306     IS.setLSUTokenID(LSU.dispatch(IR));  in dispatch()
308   if (IS.isDispatched() || (IS.isMemOp() && LSU.isWaiting(IR))) {  in dispatch()
309     LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");  in dispatch()
310     WaitSet.push_back(IR);  in dispatch()
314   if (IS.isPending() || (IS.isMemOp() && LSU.isPending(IR))) {  in dispatch()
315     LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR  in dispatch()
317     PendingSet.push_back(IR);  in dispatch()
322   assert(IS.isReady() && (!IS.isMemOp() || LSU.isReady(IR)) &&  in dispatch()
332   if (!mustIssueImmediately(IR)) {  in dispatch()
333     LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the ReadySet\n");  in dispatch()
334     ReadySet.push_back(IR);  in dispatch()