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Searched refs:CopyFromReg (Results 1 – 25 of 38) sorted by relevance

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/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Dx86_isel.ll.expected9 ; PIC-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0
18 ; WIN-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0
33 ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
43 ; WIN-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
60 ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
72 ; WIN-NEXT: t2: i16,ch = CopyFromReg t0, Register:i16 %0
90 ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
102 ; WIN-NEXT: t2: i8,ch = CopyFromReg t0, Register:i8 %0
H A Dlanai_isel.ll.expected33 ; CHECK-NEXT: t21: i32,ch = CopyFromReg t0, Register:i32 $r0
52 ; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0
75 ; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcallbr-asm-bb-exports.ll10 ; CHECK-NEXT: t4: i32,ch = CopyFromReg t0, Register:i32 %3
13 ; CHECK-NEXT: t6: i32,ch = CopyFromReg t0, Register:i32 %4
17 ; CHECK-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %2
H A Dmerge-store-partially-alias-loads.ll18 ; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
H A Dstatepoint-vreg-details.ll354 ; Test that CopyFromReg emitted during ISEL processing of gc.relocate are properly ordered w.r.t. s…
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp84 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
121 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
443 case ISD::CopyFromReg: in SUSchedulingCost()
548 case ISD::CopyFromReg: in initNumRegDefsLeft()
H A DStatepointLowering.cpp351 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
1222 SDValue CopyFromReg = getCopyFromRegs(SI, RetTy); in visitGCResult() local
1224 assert(CopyFromReg.getNode()); in visitGCResult()
1225 setValue(&CI, CopyFromReg); in visitGCResult()
H A DScheduleDAGRRList.cpp323 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
711 case ISD::CopyFromReg: in EmitNode()
1279 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2287 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2378 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2449 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2466 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3017 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
H A DInstrEmitter.cpp351 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
1103 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1190 case ISD::CopyFromReg: { in EmitSpecialNode()
H A DScheduleDAGSDNodes.cpp122 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
549 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
H A DScheduleDAGFast.cpp424 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
H A DSelectionDAGDumper.cpp171 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
H A DSelectionDAGBuilder.cpp5472 case ISD::CopyFromReg: { in getUnderlyingArgRegs()
9435 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) in visitPatchpoint()
10057 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
10590 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { in LowerArguments()
10599 if (Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
H A DSelectionDAGISel.cpp2816 case ISD::CopyFromReg: in SelectCodeCommon()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-frame-offests.ll15 ; CHECK-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp242 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
293 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
296 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DREADME-X86-64.txt46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
H A DX86InstrCompiler.td1418 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1421 // CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit
1426 N->getOpcode() != ISD::CopyFromReg &&
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h208 CopyFromReg, enumerator
H A DSelectionDAG.h779 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
789 return getNode(ISD::CopyFromReg, dl, VTs,
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfmf-propagation.ll582 ; FMFDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1
588 ; GLOBALDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td388 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
394 N->getOpcode() != ISD::CopyFromReg;
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp273 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
2215 T1.getOpcode() != ISD::CopyFromReg && in LowerSELECT()
2216 T2.getOpcode() != ISD::CopyFromReg) { in LowerSELECT()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfunction-returns.ll472 ; lowering introduces an extra CopyToReg/CopyFromReg obscuring the
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1441 if (Val.getOpcode() != ISD::CopyFromReg) in IsCopyFromSGPR()

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