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Searched refs:VT (Results 1 – 25 of 279) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2488 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOrAndImm()
2577 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOr()
2759 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertInZeroOp()
4540 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
4544 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
4548 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
4559 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
4563 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
4567 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
4578 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
[all …]
H A DAArch64ISelLowering.cpp1093 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { in AArch64TargetLowering()
1410 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) { in addTypeForNEON()
1422 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64 || in addTypeForNEON()
1461 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
7021 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) { in LowerFCOPYSIGN()
7804 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) { in LowerVAARG()
8000 (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 || in getEstimate()
10421 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || in LowerINSERT_VECTOR_ELT()
10426 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && in LowerINSERT_VECTOR_ELT()
10476 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && in LowerEXTRACT_VECTOR_ELT()
[all …]
H A DAArch64FastISel.cpp393 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
537 MVT VT; in fastMaterializeFloatZero() local
541 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
991 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
1871 MVT VT; in selectAddSub() local
2923 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2925 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2956 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
3171 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3297 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h45 bool operator==(EVT VT) const {
46 return !(*this != VT);
229 bool bitsEq(EVT VT) const { in bitsEq()
257 bool bitsGT(EVT VT) const { in bitsGT()
261 return knownBitsGT(VT); in bitsGT()
265 bool bitsGE(EVT VT) const { in bitsGE()
269 return knownBitsGE(VT); in bitsGE()
273 bool bitsLT(EVT VT) const { in bitsLT()
277 return knownBitsLT(VT); in bitsLT()
281 bool bitsLE(EVT VT) const { in bitsLE()
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H A DTargetLowering.h670 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE; in hasFastEqualityCompare()
954 return VT; in getTypeToExpandTo()
956 VT = getTypeToTransformTo(Context, VT); in getTypeToExpandTo()
1118 return (VT == MVT::Other || isTypeLegal(VT)) &&
1132 return (VT == MVT::Other || isTypeLegal(VT)) &&
1146 return (VT == MVT::Other || isTypeLegal(VT)) &&
1213 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); in isOperationExpand()
1218 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegal()
1386 assert((VT.isInteger() || VT.isFloatingPoint()) && in getTypeToPromoteTo()
1389 MVT NVT = VT; in getTypeToPromoteTo()
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H A DSelectionDAG.h104 FastID(ID), VTs(VT), NumVTs(Num) {
602 SDVTList getVTList(EVT VT);
670 return getConstantFP(Val, DL, VT, true);
689 return getFrameIndex(FI, VT, true);
811 (VT.isInteger() &&
827 (VT.isInteger() &&
951 SDValue getUNDEF(EVT VT) {
959 return getNode(ISD::VSCALE, DL, VT,
960 getConstant(MulImm.sextOrTrunc(VT.getSizeInBits()), DL, VT));
964 SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp497 switch (VT.SimpleTy) { in getOUTLINE_ATOMIC()
833 if (VT.isVector()) { in initActions()
932 assert(isTypeLegal(VT)); in canOpTrap()
958 if (VT.isSimple()) { in getTypeConversion()
978 if (!VT.isVector()) { in getTypeConversion()
1392 if (isTypeLegal(VT)) in computeRegisterProperties()
1473 if (NVT == VT) { in computeRegisterProperties()
1561 EVT PartVT = VT; in getVectorTypeBreakdown()
1657 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1671 if (VT.bitsLT(MinVT)) in GetReturnInfo()
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H A DCallingConvLower.cpp95 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
108 MVT VT = Outs[i].VT; in CheckReturn() local
110 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
122 MVT VT = Outs[i].VT; in AnalyzeReturn() local
124 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in AnalyzeReturn()
170 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
172 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
184 if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { in AnalyzeCallResult()
199 if (VT.isVector()) in isValueTypeInRegForCC()
201 if (!VT.isInteger()) in isValueTypeInRegForCC()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1285 if (VT.isVector() || !VT.isInteger()) in PromoteIntBinOp()
1353 if (VT.isVector() || !VT.isInteger()) in PromoteIntShiftOp()
1402 if (VT.isVector() || !VT.isInteger()) in PromoteExtend()
1433 if (VT.isVector() || !VT.isInteger()) in PromoteLoad()
4028 if (VT.isVector() || !VT.isInteger()) in useDivRem()
4631 if (VT.isSimple() && !VT.isVector()) { in visitSMUL_LOHI()
4674 if (VT.isSimple() && !VT.isVector()) { in visitUMUL_LOHI()
5983 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) in MatchBSwapHWordLow()
7506 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) in MatchLoadCombine()
19232 if (InVT1 != VT || InVT2 != VT) { in createBuildVecShuffle()
[all …]
H A DTargetLowering.cpp204 VT = MVT::i64; in findOptimalMemOpLowering()
220 VT = LVT; in findOptimalMemOpLowering()
233 if (VT.isVector() || VT.isFloatingPoint()) { in findOptimalMemOpLowering()
304 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) in softenSetCCOperands()
4107 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && in SimplifySetCC()
5134 if (VT.isVector() || !VT.isSimple()) in BuildSDIV()
5282 if (VT.isVector() || !VT.isSimple()) in BuildUDIV()
7126 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), in expandCTTZ()
7499 if (VT.isFloatingPoint() || VT.isVector()) { in expandUnalignedLoad()
8325 DAG.getVTList(VT, VT), in expandFixedPointDiv()
[all …]
H A DSelectionDAG.cpp934 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
1329 SDValue TrueValue = getBoolConstant(true, DL, VT, VT); in getLogicalNOT()
1698 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
1781 assert(VT == N1.getValueType() && VT == N2.getValueType() && in getVectorShuffle()
2158 if (TLI->isTypeLegal(VT) || !VT.isVector()) in getReducedAlign()
4991 assert(VT.isInteger() && VT == Operand.getValueType() && in getNode()
5699 assert((!VT.isVector() || VT == N2.getValueType()) && in getNode()
5788 assert((!VT.isVector() || VT.getVectorNumElements() == in getNode()
6081 assert((!VT.isVector() || VT.getVectorElementCount() == in getNode()
6261 if (VT != Value.getValueType() && !VT.isInteger()) in getMemsetValue()
[all …]
H A DLegalizeVectorOps.cpp627 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
914 EVT VT = Node->getValueType(0); in ExpandSELECT() local
952 if (VT.isFixedLengthVector()) in ExpandSELECT()
974 EVT VT = Node->getValueType(0); in ExpandSEXTINREG() local
996 EVT VT = Node->getValueType(0); in ExpandANY_EXTEND_VECTOR_INREG() local
1004 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1025 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
1063 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
1177 EVT VT = Mask.getValueType(); in ExpandVSELECT() local
1211 APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, VT); in ExpandVSELECT()
[all …]
H A DResourcePriorityQueue.cpp97 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
98 if (TLI->isTypeLegal(VT) in numberRCValPredInSU()
136 if (TLI->isTypeLegal(VT) in numberRCValSuccInSU()
331 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
332 if (TLI->isTypeLegal(VT) in rawRegPressureDelta()
333 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
334 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
344 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
479 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
481 if (TLI->isTypeLegal(VT)) { in scheduledNode()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp9868 if (VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 || in LowerToHorizontalOp()
10001 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) in materializeVectorConstant()
19733 (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) && in LowerFunnelShift()
22033 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 || in LowerFABSorFNEG()
22094 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 || in LowerFCOPYSIGN()
27542 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) { in LowerABS()
32103 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
37421 if (VT != MVT::v4f32 && VT != MVT::v8f32 && VT != MVT::v16f32) in combineCommutableSHUFP()
46175 if ((VT == MVT::v1i1 || VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT && in combineStore()
52159 if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f80) in getRegForInlineAsmConstraint()
[all …]
H A DX86InterleavedAccess.cpp233 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
264 assert(VT.getSizeInBits() >= 256 && in genShuffleBland()
331 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
372 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4()
421 if (VT == MVT::v16i8) { in interleave8bitStride4()
442 int VectorSize = VT.getSizeInBits(); in createShuffleStride()
443 int VF = VT.getVectorNumElements(); in createShuffleStride()
564 createShuffleStride(VT, 3, VPShuf); in deinterleave8bitStride3()
565 setGroupSize(VT, GroupSize); in deinterleave8bitStride3()
615 int VF = VT.getVectorNumElements(); in group2Shuffle()
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H A DX86ISelLowering.h938 bool isSafeMemOpType(MVT VT) const override;
1001 return VT == MVT::f32 || VT == MVT::f64 || VT.isVector(); in hasBitPreservingFPLogic()
1045 auto VTIsOk = [](EVT VT) -> bool { in shouldTransformSignedTruncationCheck()
1046 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || in shouldTransformSignedTruncationCheck()
1047 VT == MVT::i64; in shouldTransformSignedTruncationCheck()
1061 return VT.isScalarInteger(); in convertSetCCLogicToBitwiseLogic()
1069 EVT VT) const override;
1249 bool isFPImmLegal(const APFloat &Imm, EVT VT,
1273 return !X86ScalarSSEf64 || VT == MVT::f80; in ShouldShrinkFPConstant()
1283 bool isScalarFPTypeInSSEReg(EVT VT) const { in isScalarFPTypeInSSEReg() argument
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp876 if (!VT.isVector()) in getSetCCResultType()
1275 assert(((VT.isFixedLengthVector() && TLI.isTypeLegal(VT)) || in getContainerForFixedLengthVector()
2315 if (!VT.isVector() || VT.getVectorElementType() != MVT::f64 || in LowerOperation()
2355 if (!VT.isVector() || VT.getVectorElementType() != MVT::f16 || in LowerOperation()
4322 VT = MVT::v8i1; in lowerFixedLengthVectorStoreToRVV()
5015 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && in ReplaceNodeResults()
5083 assert(VT.isInteger() && !VT.isVector() && "Unexpected VT!"); in ReplaceNodeResults()
5146 assert((VT == MVT::i8 || VT == MVT::i16 || in ReplaceNodeResults()
5591 if (VT != MVT::i32 && VT != Subtarget.getXLenVT()) in combineORToSHFL()
8184 MVT VT = Outs[i].VT; in CanLowerReturn() local
[all …]
H A DRISCVISelDAGToDAG.cpp57 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
61 assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && in PreprocessISelDAG()
240 MVT VT = Node->getSimpleValueType(0); in selectVLSEG() local
280 MVT VT = Node->getSimpleValueType(0); in selectVLSEGFF() local
325 MVT VT = Node->getSimpleValueType(0); in selectVLXSEG() local
1269 if (VT.isFixedLengthVector()) in Select()
1270 VT = TLI.getContainerForFixedLengthVector(VT); in Select()
1318 MVT SubVecContainerVT = VT; in Select()
1320 if (VT.isFixedLengthVector()) in Select()
1472 MVT VT = N.getSimpleValueType(); in selectSExti32() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp141 if (VT == MVT::i64) in AMDGPUTargetLowering()
890 return VT == MVT::f32 || VT == MVT::f64 || in isFAbsFree()
897 VT = VT.getScalarType(); in isFNegFree()
898 return VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f16; in isFNegFree()
1399 if (VT == MVT::v4i16 || VT == MVT::v4f16) { in LowerCONCAT_VECTORS()
1748 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); in LowerDIVREM24()
2017 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); in LowerUDIVREM64()
2946 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT)) in shouldCombineMemoryType()
3192 if (VT != MVT::i64) in performShlCombine()
3275 if (VT != MVT::i64) in performSrlCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp911 if (VT != MVT::i8 && VT != MVT::i16) { in getPreIndexedAddressParts()
962 if (VT != MVT::i8 && VT != MVT::i16) { in getPostIndexedAddressParts()
1031 MVT VT = Args[i].VT; in analyzeArguments() local
1057 MVT VT = Args[i].VT; in analyzeArguments() local
1118 MVT VT = Args[i].VT; in analyzeReturnValues() local
1942 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1958 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1974 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1979 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1984 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp207 VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
1839 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8)) || in getSetCCResultType()
1891 if (VT == MVT::Glue || VT == MVT::Other) in getSchedulingPreference()
5768 if (VT != MVT::v4i16 && VT != MVT::v8i16) in LowerVectorFP_TO_INT()
6374 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || in LowerCTPOP()
6375 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && in LowerCTPOP()
8387 assert((VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i8) && in LowerVECTOR_SHUFFLEUsingMovs()
8942 assert((VT == MVT::v16i1 || VT == MVT::v8i1 || VT == MVT::v4i1) && in LowerTruncatei1()
13999 (VT == MVT::v4i1 || VT == MVT::v8i1 || VT == MVT::v16i1)) in PerformORCombine()
18518 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { in getARMIndexedAddressParts()
[all …]
H A DARMFastISel.cpp455 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) in ARMMaterializeInt()
649 MVT VT; in fastMaterializeAlloca() local
690 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isLoadTypeLegal()
1024 MVT VT; in SelectLoad() local
1156 MVT VT; in SelectStore() local
1600 MVT VT; in SelectSelect() local
1676 MVT VT; in SelectDiv() local
1705 MVT VT; in SelectRem() local
1793 bool is64bit = VT == MVT::f64 || VT == MVT::i64; in SelectBinaryFPOp()
2446 MVT VT; in ARMTryEmitSmallMemCpy() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Support/
H A DLowLevelType.cpp18 LLT::LLT(MVT VT) { in LLT() argument
19 if (VT.isVector()) { in LLT()
20 bool asVector = VT.getVectorNumElements() > 1; in LLT()
22 VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(), in LLT()
24 } else if (VT.isValid()) { in LLT()
28 ElementCount::getFixed(0), VT.getSizeInBits(), /*AddressSpace=*/0); in LLT()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp41 for (EVT VT : VTs) { in computeLegalValueVTs() local
42 unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT); in computeLegalValueVTs()
43 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT); in computeLegalValueVTs()
114 for (auto VT : MFI.getParams()) in WebAssemblyFunctionInfo() local
115 Params.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo()
116 for (auto VT : MFI.getResults()) in WebAssemblyFunctionInfo() local
117 Results.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo()
144 for (auto VT : YamlMFI.Params) in initializeBaseYamlFields() local
145 addParam(WebAssembly::parseMVT(VT.Value)); in initializeBaseYamlFields()
146 for (auto VT : YamlMFI.Results) in initializeBaseYamlFields() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp85 if (VT == MVT::i32) { in BPFTargetLowering()
99 for (auto VT : { MVT::i32, MVT::i64 }) { in BPFTargetLowering()
100 if (VT == MVT::i32 && !STI.getHasAlu32()) in BPFTargetLowering()
105 setOperationAction(ISD::SREM, VT, Expand); in BPFTargetLowering()
106 setOperationAction(ISD::UREM, VT, Expand); in BPFTargetLowering()
107 setOperationAction(ISD::MULHU, VT, Expand); in BPFTargetLowering()
108 setOperationAction(ISD::MULHS, VT, Expand); in BPFTargetLowering()
111 setOperationAction(ISD::ROTR, VT, Expand); in BPFTargetLowering()
112 setOperationAction(ISD::ROTL, VT, Expand); in BPFTargetLowering()
116 setOperationAction(ISD::CTPOP, VT, Expand); in BPFTargetLowering()
[all …]

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