Lines Matching refs:VT
59 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
61 setLoadExtAction(N, VT, MVT::i1, Promote); in AVRTargetLowering()
62 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
68 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
69 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
70 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
71 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
72 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
134 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); in AVRTargetLowering()
136 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); in AVRTargetLowering()
137 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); in AVRTargetLowering()
138 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); in AVRTargetLowering()
139 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); in AVRTargetLowering()
140 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); in AVRTargetLowering()
141 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); in AVRTargetLowering()
177 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
178 setOperationAction(ISD::MULHS, VT, Expand); in AVRTargetLowering()
179 setOperationAction(ISD::MULHU, VT, Expand); in AVRTargetLowering()
182 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
183 setOperationAction(ISD::CTPOP, VT, Expand); in AVRTargetLowering()
184 setOperationAction(ISD::CTLZ, VT, Expand); in AVRTargetLowering()
185 setOperationAction(ISD::CTTZ, VT, Expand); in AVRTargetLowering()
188 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in AVRTargetLowering()
266 EVT VT) const { in getSetCCResultType()
267 assert(!VT.isVector() && "No AVR SetCC type for vectors!"); in getSetCCResultType()
276 EVT VT = Op.getValueType(); in LowerShifts() local
278 assert(isPowerOf2_32(VT.getSizeInBits()) && in LowerShifts()
287 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0), in LowerShifts()
290 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0), in LowerShifts()
296 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
297 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt); in LowerShifts()
303 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
304 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt); in LowerShifts()
307 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0), in LowerShifts()
321 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
325 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
338 if (VT.getSizeInBits() == 8) { in LowerShifts()
341 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); in LowerShifts()
343 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT)); in LowerShifts()
348 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); in LowerShifts()
350 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT)); in LowerShifts()
354 Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim, in LowerShifts()
355 DAG.getConstant(7, dl, VT)); in LowerShifts()
359 Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim, in LowerShifts()
360 DAG.getConstant(7, dl, VT)); in LowerShifts()
364 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, in LowerShifts()
365 DAG.getConstant(7, dl, VT)); in LowerShifts()
368 } else if (VT.getSizeInBits() == 16) { in LowerShifts()
372 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, in LowerShifts()
373 DAG.getConstant(4, dl, VT)); in LowerShifts()
377 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, in LowerShifts()
378 DAG.getConstant(4, dl, VT)); in LowerShifts()
387 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, in LowerShifts()
388 DAG.getConstant(8, dl, VT)); in LowerShifts()
392 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, in LowerShifts()
393 DAG.getConstant(8, dl, VT)); in LowerShifts()
397 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, in LowerShifts()
398 DAG.getConstant(8, dl, VT)); in LowerShifts()
407 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, in LowerShifts()
408 DAG.getConstant(12, dl, VT)); in LowerShifts()
412 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, in LowerShifts()
413 DAG.getConstant(12, dl, VT)); in LowerShifts()
422 Victim = DAG.getNode(Opc8, dl, VT, Victim); in LowerShifts()
433 EVT VT = Op->getValueType(0); in LowerDivRem() local
434 Type *Ty = VT.getTypeForEVT(*DAG.getContext()); in LowerDivRem()
437 switch (VT.getSimpleVT().SimpleTy) { in LowerDivRem()
560 EVT VT = LHS.getValueType(); in getAVRCmp() local
586 LHS = DAG.getConstant(0, DL, VT); in getAVRCmp()
593 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); in getAVRCmp()
612 LHS = DAG.getConstant(0, DL, VT); in getAVRCmp()
637 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); in getAVRCmp()
650 if (VT == MVT::i32) { in getAVRCmp()
669 } else if (VT == MVT::i64) { in getAVRCmp()
709 } else if (VT == MVT::i8 || VT == MVT::i16) { in getAVRCmp()
713 (VT == MVT::i8) in getAVRCmp()
889 EVT VT; in getPreIndexedAddressParts() local
894 VT = LD->getMemoryVT(); in getPreIndexedAddressParts()
902 VT = ST->getMemoryVT(); in getPreIndexedAddressParts()
911 if (VT != MVT::i8 && VT != MVT::i16) { in getPreIndexedAddressParts()
924 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { in getPreIndexedAddressParts()
946 EVT VT; in getPostIndexedAddressParts() local
950 VT = LD->getMemoryVT(); in getPostIndexedAddressParts()
954 VT = ST->getMemoryVT(); in getPostIndexedAddressParts()
962 if (VT != MVT::i8 && VT != MVT::i16) { in getPostIndexedAddressParts()
974 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { in getPostIndexedAddressParts()
1031 MVT VT = Args[i].VT; in analyzeArguments() local
1037 unsigned TotalBytes = VT.getStoreSize(); in analyzeArguments()
1042 TotalBytes += Args[j].VT.getStoreSize(); in analyzeArguments()
1057 MVT VT = Args[i].VT; in analyzeArguments() local
1060 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext()); in analyzeArguments()
1064 CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full)); in analyzeArguments()
1067 if (VT == MVT::i8) { in analyzeArguments()
1069 } else if (VT == MVT::i16) { in analyzeArguments()
1076 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); in analyzeArguments()
1079 RegIdx -= VT.getStoreSize(); in analyzeArguments()
1091 TotalBytes += Arg.VT.getStoreSize(); in getTotalArgumentsSizeInBytes()
1118 MVT VT = Args[i].VT; in analyzeReturnValues() local
1120 if (VT == MVT::i8) { in analyzeReturnValues()
1122 } else if (VT == MVT::i16) { in analyzeReturnValues()
1128 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); in analyzeReturnValues()
1130 RegIdx -= VT.getStoreSize(); in analyzeReturnValues()
1932 MVT VT) const { in getRegForInlineAsmConstraint()
1936 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
1938 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
1942 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1946 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
1948 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
1952 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
1954 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
1958 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1964 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
1966 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
1970 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
1974 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1979 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1984 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1989 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
1998 Subtarget.getRegisterInfo(), Constraint, VT); in getRegForInlineAsmConstraint()
2108 Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT, in getRegisterByName() argument
2112 if (VT == LLT::scalar(8)) { in getRegisterByName()