Lines Matching refs:VT
182 bool isTypeLegal(Type *Ty, MVT &VT);
183 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
187 bool simplifyAddress(Address &Addr, MVT VT);
225 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
227 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
229 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
236 unsigned emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm);
265 unsigned materializeInt(const ConstantInt *CI, MVT VT);
266 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
318 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
319 switch (VT.SimpleTy) { in getImplicitScaleFactor()
370 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) { in materializeInt() argument
371 if (VT > MVT::i64) in materializeInt()
375 return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in materializeInt()
378 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
387 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP() argument
393 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
397 bool Is64Bit = (VT == MVT::f64); in materializeFP()
404 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
417 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
435 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
516 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
520 assert(VT == MVT::i64 && "Expected 64-bit pointers"); in fastMaterializeConstant()
521 return materializeInt(ConstantInt::get(Type::getInt64Ty(*Context), 0), VT); in fastMaterializeConstant()
525 return materializeInt(CI, VT); in fastMaterializeConstant()
527 return materializeFP(CFP, VT); in fastMaterializeConstant()
537 MVT VT; in fastMaterializeFloatZero() local
538 if (!isTypeLegal(CFP->getType(), VT)) in fastMaterializeFloatZero()
541 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
544 bool Is64Bit = (VT == MVT::f64); in fastMaterializeFloatZero()
547 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg); in fastMaterializeFloatZero()
958 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal() argument
967 VT = evt.getSimpleVT(); in isTypeLegal()
970 if (VT == MVT::f128) in isTypeLegal()
975 return TLI.isTypeLegal(VT); in isTypeLegal()
982 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) { in isTypeSupported() argument
986 if (isTypeLegal(Ty, VT)) in isTypeSupported()
991 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
1005 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) { in simplifyAddress() argument
1009 unsigned ScaleFactor = getImplicitScaleFactor(VT); in simplifyAddress()
1453 MVT VT = EVT.getSimpleVT(); in emitCmp() local
1455 switch (VT.SimpleTy) { in emitCmp()
1463 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1466 return emitFCmp(VT, LHS, RHS); in emitCmp()
1525 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm) { in emitAdd_ri_() argument
1528 ResultReg = emitAddSub_ri(false, VT, Op0, -Imm); in emitAdd_ri_()
1530 ResultReg = emitAddSub_ri(true, VT, Op0, Imm); in emitAdd_ri_()
1535 unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm); in emitAdd_ri_()
1539 ResultReg = emitAddSub_rr(true, VT, Op0, CReg); in emitAdd_ri_()
1632 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp() local
1633 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg); in emitLogicalOp()
1733 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad() argument
1735 if (!TLI.allowsMisalignedMemoryAccesses(VT)) in emitLoad()
1739 if (!simplifyAddress(Addr, VT)) in emitLoad()
1742 unsigned ScaleFactor = getImplicitScaleFactor(VT); in emitLoad()
1810 switch (VT.SimpleTy) { in emitLoad()
1850 if (VT == MVT::i1) { in emitLoad()
1858 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
1871 MVT VT; in selectAddSub() local
1872 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectAddSub()
1875 if (VT.isVector()) in selectAddSub()
1883 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1886 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1897 MVT VT; in selectLogicalOp() local
1898 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectLogicalOp()
1901 if (VT.isVector()) in selectLogicalOp()
1909 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1912 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1915 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1926 MVT VT; in selectLoad() local
1930 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) || in selectLoad()
1956 MVT RetVT = VT; in selectLoad()
1963 RetVT = VT; in selectLoad()
1968 RetVT = VT; in selectLoad()
1974 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I)); in selectLoad()
1997 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
2036 bool AArch64FastISel::emitStoreRelease(MVT VT, unsigned SrcReg, in emitStoreRelease() argument
2040 switch (VT.SimpleTy) { in emitStoreRelease()
2058 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr, in emitStore() argument
2060 if (!TLI.allowsMisalignedMemoryAccesses(VT)) in emitStore()
2064 if (!simplifyAddress(Addr, VT)) in emitStore()
2067 unsigned ScaleFactor = getImplicitScaleFactor(VT); in emitStore()
2099 switch (VT.SimpleTy) { in emitStore()
2127 MVT VT; in selectStore() local
2132 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true)) in selectStore()
2155 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2158 VT = MVT::getIntegerVT(VT.getSizeInBits()); in selectStore()
2159 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2178 return emitStoreRelease(VT, SrcReg, AddrReg, in selectStore()
2188 if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I))) in selectStore()
2255 MVT VT; in emitCompareAndBranch() local
2256 if (!isTypeSupported(LHS->getType(), VT)) in emitCompareAndBranch()
2259 unsigned BW = VT.getSizeInBits(); in emitCompareAndBranch()
2301 if (VT == MVT::i1) in emitCompareAndBranch()
2350 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*isZExt=*/true); in emitCompareAndBranch()
2652 MVT VT; in selectSelect() local
2653 if (!isTypeSupported(I->getType(), VT)) in selectSelect()
2658 switch (VT.SimpleTy) { in selectSelect()
2915 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments() local
2916 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8()) in fastLowerArguments()
2919 if (VT.isVector() && in fastLowerArguments()
2923 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2925 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2926 VT.is128BitVector()) in fastLowerArguments()
2953 MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); in fastLowerArguments() local
2956 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
2959 VT = MVT::i32; in fastLowerArguments()
2960 } else if (VT == MVT::i64) { in fastLowerArguments()
2963 } else if (VT == MVT::f16) { in fastLowerArguments()
2966 } else if (VT == MVT::f32) { in fastLowerArguments()
2969 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
2972 } else if (VT.is128BitVector()) { in fastLowerArguments()
3169 MVT VT; in fastLowerCall() local
3170 if (!isTypeLegal(Val->getType(), VT) && in fastLowerCall()
3171 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3175 if (VT.isVector() || VT.getSizeInBits() > 64) in fastLowerCall()
3178 OutVTs.push_back(VT); in fastLowerCall()
3275 MVT VT; in tryEmitSmallMemCpy() local
3278 VT = MVT::i64; in tryEmitSmallMemCpy()
3280 VT = MVT::i32; in tryEmitSmallMemCpy()
3282 VT = MVT::i16; in tryEmitSmallMemCpy()
3284 VT = MVT::i8; in tryEmitSmallMemCpy()
3289 VT = MVT::i32; in tryEmitSmallMemCpy()
3291 VT = MVT::i16; in tryEmitSmallMemCpy()
3293 VT = MVT::i8; in tryEmitSmallMemCpy()
3297 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy()
3301 if (!emitStore(VT, ResultReg, Dest)) in tryEmitSmallMemCpy()
3304 int64_t Size = VT.getSizeInBits() / 8; in tryEmitSmallMemCpy()
3556 MVT VT; in fastLowerIntrinsicCall() local
3557 if (!isTypeLegal(II->getType(), VT)) in fastLowerIntrinsicCall()
3561 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3574 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3592 MVT VT; in fastLowerIntrinsicCall() local
3593 if (!isTypeLegal(RetTy, VT)) in fastLowerIntrinsicCall()
3600 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg); in fastLowerIntrinsicCall()
3618 MVT VT; in fastLowerIntrinsicCall() local
3619 if (!isTypeLegal(RetTy, VT)) in fastLowerIntrinsicCall()
3622 if (VT != MVT::i32 && VT != MVT::i64) in fastLowerIntrinsicCall()
3657 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3661 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3665 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3669 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3682 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3685 fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32); in fastLowerIntrinsicCall()
3692 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3695 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3696 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3697 emitSubs_rs(VT, SMULHReg, MulReg, AArch64_AM::ASR, 63, in fastLowerIntrinsicCall()
3712 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3719 MulReg = fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32); in fastLowerIntrinsicCall()
3721 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3724 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3725 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3726 emitSubs_rr(VT, AArch64::XZR, UMULHReg, /*WantResult=*/false); in fastLowerIntrinsicCall()
3733 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
4566 MVT VT; in selectMul() local
4567 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectMul()
4570 if (VT.isVector()) in selectMul()
4583 MVT SrcVT = VT; in selectMul()
4587 MVT VT; in selectMul() local
4588 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) { in selectMul()
4589 SrcVT = VT; in selectMul()
4596 MVT VT; in selectMul() local
4597 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) { in selectMul()
4598 SrcVT = VT; in selectMul()
4610 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4626 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg); in selectMul()
4800 MVT VT; in selectSDiv() local
4801 if (!isTypeLegal(I->getType(), VT)) in selectSDiv()
4808 if ((VT != MVT::i32 && VT != MVT::i64) || !C || in selectSDiv()
4818 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2); in selectSDiv()
4826 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()
4831 if (!emitICmp_ri(VT, Src0Reg, 0)) in selectSDiv()
4836 if (VT == MVT::i64) { in selectSDiv()
4850 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv()
4853 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
4856 ResultReg = emitASR_ri(VT, VT, SelectReg, Lg2); in selectSDiv()
4899 MVT VT = TLI.getPointerTy(DL); in selectGetElementPtr() local
4921 N = emitAdd_ri_(VT, N, TotalOffs); in selectGetElementPtr()
4934 unsigned C = fastEmit_i(VT, VT, ISD::Constant, ElementSize); in selectGetElementPtr()
4937 IdxN = emitMul_rr(VT, IdxN, C); in selectGetElementPtr()
4941 N = fastEmit_rr(VT, VT, ISD::ADD, N, IdxN); in selectGetElementPtr()
4947 N = emitAdd_ri_(VT, N, TotalOffs); in selectGetElementPtr()
4964 MVT VT; in selectAtomicCmpXchg() local
4965 if (!isTypeLegal(RetTy, VT)) in selectAtomicCmpXchg()
4972 if (VT == MVT::i32) { in selectAtomicCmpXchg()
4976 } else if (VT == MVT::i64) { in selectAtomicCmpXchg()
5006 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR) in selectAtomicCmpXchg()