Lines Matching refs:VT
111 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering() argument
112 unsigned Size = VT.getSizeInBits().getKnownMinValue(); in RISCVTargetLowering()
124 addRegisterClass(VT, RC); in RISCVTargetLowering()
127 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
128 addRegClassForRVV(VT); in RISCVTargetLowering()
129 for (MVT VT : IntVecVTs) in RISCVTargetLowering() local
130 addRegClassForRVV(VT); in RISCVTargetLowering()
133 for (MVT VT : F16VecVTs) in RISCVTargetLowering() local
134 addRegClassForRVV(VT); in RISCVTargetLowering()
137 for (MVT VT : F32VecVTs) in RISCVTargetLowering() local
138 addRegClassForRVV(VT); in RISCVTargetLowering()
141 for (MVT VT : F64VecVTs) in RISCVTargetLowering() local
142 addRegClassForRVV(VT); in RISCVTargetLowering()
145 auto addRegClassForFixedVectors = [this](MVT VT) { in RISCVTargetLowering() argument
146 MVT ContainerVT = getContainerForFixedLengthVector(VT); in RISCVTargetLowering()
149 addRegisterClass(VT, TRI.getRegClass(RCID)); in RISCVTargetLowering()
151 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in RISCVTargetLowering() local
152 if (useRVVForFixedLengthVectorVT(VT)) in RISCVTargetLowering()
153 addRegClassForFixedVectors(VT); in RISCVTargetLowering()
155 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) in RISCVTargetLowering() local
156 if (useRVVForFixedLengthVectorVT(VT)) in RISCVTargetLowering()
157 addRegClassForFixedVectors(VT); in RISCVTargetLowering()
454 for (MVT VT : BoolVecVTs) { in RISCVTargetLowering() local
455 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
458 setOperationAction(ISD::TRUNCATE, VT, Custom); in RISCVTargetLowering()
459 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
460 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
461 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
463 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
464 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
466 setOperationAction(ISD::SELECT, VT, Custom); in RISCVTargetLowering()
467 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
468 setOperationAction(ISD::VSELECT, VT, Expand); in RISCVTargetLowering()
470 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in RISCVTargetLowering()
471 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in RISCVTargetLowering()
472 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in RISCVTargetLowering()
478 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in RISCVTargetLowering()
479 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in RISCVTargetLowering()
480 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
481 setOperationAction(ISD::FP_TO_UINT, VT, Custom); in RISCVTargetLowering()
486 setTruncStoreAction(OtherVT, VT, Expand); in RISCVTargetLowering()
487 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
488 setLoadExtAction(ISD::SEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
489 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
493 for (MVT VT : IntVecVTs) { in RISCVTargetLowering() local
494 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
495 setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom); in RISCVTargetLowering()
497 setOperationAction(ISD::SMIN, VT, Legal); in RISCVTargetLowering()
498 setOperationAction(ISD::SMAX, VT, Legal); in RISCVTargetLowering()
499 setOperationAction(ISD::UMIN, VT, Legal); in RISCVTargetLowering()
500 setOperationAction(ISD::UMAX, VT, Legal); in RISCVTargetLowering()
502 setOperationAction(ISD::ROTL, VT, Expand); in RISCVTargetLowering()
503 setOperationAction(ISD::ROTR, VT, Expand); in RISCVTargetLowering()
506 setOperationAction(ISD::ANY_EXTEND, VT, Custom); in RISCVTargetLowering()
507 setOperationAction(ISD::SIGN_EXTEND, VT, Custom); in RISCVTargetLowering()
508 setOperationAction(ISD::ZERO_EXTEND, VT, Custom); in RISCVTargetLowering()
514 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in RISCVTargetLowering()
515 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in RISCVTargetLowering()
516 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
517 setOperationAction(ISD::FP_TO_UINT, VT, Custom); in RISCVTargetLowering()
519 setOperationAction(ISD::SADDSAT, VT, Legal); in RISCVTargetLowering()
520 setOperationAction(ISD::UADDSAT, VT, Legal); in RISCVTargetLowering()
521 setOperationAction(ISD::SSUBSAT, VT, Legal); in RISCVTargetLowering()
522 setOperationAction(ISD::USUBSAT, VT, Legal); in RISCVTargetLowering()
526 setOperationAction(ISD::TRUNCATE, VT, Custom); in RISCVTargetLowering()
529 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
530 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
534 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in RISCVTargetLowering()
535 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in RISCVTargetLowering()
536 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in RISCVTargetLowering()
537 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in RISCVTargetLowering()
538 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in RISCVTargetLowering()
539 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in RISCVTargetLowering()
540 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in RISCVTargetLowering()
541 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in RISCVTargetLowering()
544 setOperationAction(VPOpc, VT, Custom); in RISCVTargetLowering()
546 setOperationAction(ISD::LOAD, VT, Custom); in RISCVTargetLowering()
547 setOperationAction(ISD::STORE, VT, Custom); in RISCVTargetLowering()
549 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
550 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
551 setOperationAction(ISD::MGATHER, VT, Custom); in RISCVTargetLowering()
552 setOperationAction(ISD::MSCATTER, VT, Custom); in RISCVTargetLowering()
554 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
555 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
556 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
558 setOperationAction(ISD::SELECT, VT, Custom); in RISCVTargetLowering()
559 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
561 setOperationAction(ISD::STEP_VECTOR, VT, Custom); in RISCVTargetLowering()
562 setOperationAction(ISD::VECTOR_REVERSE, VT, Custom); in RISCVTargetLowering()
565 setTruncStoreAction(VT, OtherVT, Expand); in RISCVTargetLowering()
566 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
567 setLoadExtAction(ISD::SEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
568 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
586 const auto SetCommonVFPActions = [&](MVT VT) { in RISCVTargetLowering() argument
587 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
592 setOperationAction(ISD::FP_ROUND, VT, Custom); in RISCVTargetLowering()
593 setOperationAction(ISD::FP_EXTEND, VT, Custom); in RISCVTargetLowering()
595 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
596 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
599 setCondCodeAction(CC, VT, Expand); in RISCVTargetLowering()
601 setOperationAction(ISD::FMINNUM, VT, Legal); in RISCVTargetLowering()
602 setOperationAction(ISD::FMAXNUM, VT, Legal); in RISCVTargetLowering()
604 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in RISCVTargetLowering()
605 setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom); in RISCVTargetLowering()
606 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in RISCVTargetLowering()
607 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in RISCVTargetLowering()
608 setOperationAction(ISD::FCOPYSIGN, VT, Legal); in RISCVTargetLowering()
610 setOperationAction(ISD::LOAD, VT, Custom); in RISCVTargetLowering()
611 setOperationAction(ISD::STORE, VT, Custom); in RISCVTargetLowering()
613 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
614 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
615 setOperationAction(ISD::MGATHER, VT, Custom); in RISCVTargetLowering()
616 setOperationAction(ISD::MSCATTER, VT, Custom); in RISCVTargetLowering()
618 setOperationAction(ISD::SELECT, VT, Custom); in RISCVTargetLowering()
619 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
621 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
622 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
623 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
625 setOperationAction(ISD::VECTOR_REVERSE, VT, Custom); in RISCVTargetLowering()
628 setOperationAction(VPOpc, VT, Custom); in RISCVTargetLowering()
634 [&](MVT VT, ArrayRef<MVT::SimpleValueType> SmallerVTs) { in RISCVTargetLowering() argument
636 setTruncStoreAction(VT, SmallVT, Expand); in RISCVTargetLowering()
637 setLoadExtAction(ISD::EXTLOAD, VT, SmallVT, Expand); in RISCVTargetLowering()
642 for (MVT VT : F16VecVTs) in RISCVTargetLowering() local
643 SetCommonVFPActions(VT); in RISCVTargetLowering()
645 for (MVT VT : F32VecVTs) { in RISCVTargetLowering() local
647 SetCommonVFPActions(VT); in RISCVTargetLowering()
648 SetCommonVFPExtLoadTruncStoreActions(VT, F16VecVTs); in RISCVTargetLowering()
651 for (MVT VT : F64VecVTs) { in RISCVTargetLowering() local
653 SetCommonVFPActions(VT); in RISCVTargetLowering()
654 SetCommonVFPExtLoadTruncStoreActions(VT, F16VecVTs); in RISCVTargetLowering()
655 SetCommonVFPExtLoadTruncStoreActions(VT, F32VecVTs); in RISCVTargetLowering()
659 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { in RISCVTargetLowering() local
660 if (!useRVVForFixedLengthVectorVT(VT)) in RISCVTargetLowering()
665 setOperationAction(Op, VT, Expand); in RISCVTargetLowering()
667 setTruncStoreAction(VT, OtherVT, Expand); in RISCVTargetLowering()
668 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
669 setLoadExtAction(ISD::SEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
670 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
674 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
675 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
677 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in RISCVTargetLowering()
678 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
680 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
683 setOperationAction(ISD::LOAD, VT, Custom); in RISCVTargetLowering()
684 setOperationAction(ISD::STORE, VT, Custom); in RISCVTargetLowering()
686 setOperationAction(ISD::SETCC, VT, Custom); in RISCVTargetLowering()
688 setOperationAction(ISD::SELECT, VT, Custom); in RISCVTargetLowering()
690 setOperationAction(ISD::TRUNCATE, VT, Custom); in RISCVTargetLowering()
692 setOperationAction(ISD::BITCAST, VT, Custom); in RISCVTargetLowering()
694 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in RISCVTargetLowering()
695 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in RISCVTargetLowering()
696 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in RISCVTargetLowering()
698 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in RISCVTargetLowering()
699 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in RISCVTargetLowering()
700 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
701 setOperationAction(ISD::FP_TO_UINT, VT, Custom); in RISCVTargetLowering()
704 if (VT.getVectorElementType() == MVT::i1) { in RISCVTargetLowering()
705 setOperationAction(ISD::AND, VT, Custom); in RISCVTargetLowering()
706 setOperationAction(ISD::OR, VT, Custom); in RISCVTargetLowering()
707 setOperationAction(ISD::XOR, VT, Custom); in RISCVTargetLowering()
715 if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) { in RISCVTargetLowering()
716 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
717 setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom); in RISCVTargetLowering()
720 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in RISCVTargetLowering()
721 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
723 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
724 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
725 setOperationAction(ISD::MGATHER, VT, Custom); in RISCVTargetLowering()
726 setOperationAction(ISD::MSCATTER, VT, Custom); in RISCVTargetLowering()
727 setOperationAction(ISD::ADD, VT, Custom); in RISCVTargetLowering()
728 setOperationAction(ISD::MUL, VT, Custom); in RISCVTargetLowering()
729 setOperationAction(ISD::SUB, VT, Custom); in RISCVTargetLowering()
730 setOperationAction(ISD::AND, VT, Custom); in RISCVTargetLowering()
731 setOperationAction(ISD::OR, VT, Custom); in RISCVTargetLowering()
732 setOperationAction(ISD::XOR, VT, Custom); in RISCVTargetLowering()
733 setOperationAction(ISD::SDIV, VT, Custom); in RISCVTargetLowering()
734 setOperationAction(ISD::SREM, VT, Custom); in RISCVTargetLowering()
735 setOperationAction(ISD::UDIV, VT, Custom); in RISCVTargetLowering()
736 setOperationAction(ISD::UREM, VT, Custom); in RISCVTargetLowering()
737 setOperationAction(ISD::SHL, VT, Custom); in RISCVTargetLowering()
738 setOperationAction(ISD::SRA, VT, Custom); in RISCVTargetLowering()
739 setOperationAction(ISD::SRL, VT, Custom); in RISCVTargetLowering()
741 setOperationAction(ISD::SMIN, VT, Custom); in RISCVTargetLowering()
742 setOperationAction(ISD::SMAX, VT, Custom); in RISCVTargetLowering()
743 setOperationAction(ISD::UMIN, VT, Custom); in RISCVTargetLowering()
744 setOperationAction(ISD::UMAX, VT, Custom); in RISCVTargetLowering()
745 setOperationAction(ISD::ABS, VT, Custom); in RISCVTargetLowering()
747 setOperationAction(ISD::MULHS, VT, Custom); in RISCVTargetLowering()
748 setOperationAction(ISD::MULHU, VT, Custom); in RISCVTargetLowering()
750 setOperationAction(ISD::SADDSAT, VT, Custom); in RISCVTargetLowering()
751 setOperationAction(ISD::UADDSAT, VT, Custom); in RISCVTargetLowering()
752 setOperationAction(ISD::SSUBSAT, VT, Custom); in RISCVTargetLowering()
753 setOperationAction(ISD::USUBSAT, VT, Custom); in RISCVTargetLowering()
755 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
756 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
758 setOperationAction(ISD::ANY_EXTEND, VT, Custom); in RISCVTargetLowering()
759 setOperationAction(ISD::SIGN_EXTEND, VT, Custom); in RISCVTargetLowering()
760 setOperationAction(ISD::ZERO_EXTEND, VT, Custom); in RISCVTargetLowering()
764 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in RISCVTargetLowering()
765 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in RISCVTargetLowering()
766 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in RISCVTargetLowering()
767 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in RISCVTargetLowering()
768 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in RISCVTargetLowering()
771 setOperationAction(VPOpc, VT, Custom); in RISCVTargetLowering()
774 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { in RISCVTargetLowering() local
775 if (!useRVVForFixedLengthVectorVT(VT)) in RISCVTargetLowering()
780 setOperationAction(Op, VT, Expand); in RISCVTargetLowering()
782 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
783 setTruncStoreAction(VT, OtherVT, Expand); in RISCVTargetLowering()
787 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
788 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
790 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in RISCVTargetLowering()
791 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in RISCVTargetLowering()
792 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
795 setOperationAction(ISD::LOAD, VT, Custom); in RISCVTargetLowering()
796 setOperationAction(ISD::STORE, VT, Custom); in RISCVTargetLowering()
797 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
798 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
799 setOperationAction(ISD::MGATHER, VT, Custom); in RISCVTargetLowering()
800 setOperationAction(ISD::MSCATTER, VT, Custom); in RISCVTargetLowering()
801 setOperationAction(ISD::FADD, VT, Custom); in RISCVTargetLowering()
802 setOperationAction(ISD::FSUB, VT, Custom); in RISCVTargetLowering()
803 setOperationAction(ISD::FMUL, VT, Custom); in RISCVTargetLowering()
804 setOperationAction(ISD::FDIV, VT, Custom); in RISCVTargetLowering()
805 setOperationAction(ISD::FNEG, VT, Custom); in RISCVTargetLowering()
806 setOperationAction(ISD::FABS, VT, Custom); in RISCVTargetLowering()
807 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in RISCVTargetLowering()
808 setOperationAction(ISD::FSQRT, VT, Custom); in RISCVTargetLowering()
809 setOperationAction(ISD::FMA, VT, Custom); in RISCVTargetLowering()
810 setOperationAction(ISD::FMINNUM, VT, Custom); in RISCVTargetLowering()
811 setOperationAction(ISD::FMAXNUM, VT, Custom); in RISCVTargetLowering()
813 setOperationAction(ISD::FP_ROUND, VT, Custom); in RISCVTargetLowering()
814 setOperationAction(ISD::FP_EXTEND, VT, Custom); in RISCVTargetLowering()
817 setCondCodeAction(CC, VT, Expand); in RISCVTargetLowering()
819 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
820 setOperationAction(ISD::SELECT, VT, Custom); in RISCVTargetLowering()
821 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
823 setOperationAction(ISD::BITCAST, VT, Custom); in RISCVTargetLowering()
825 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in RISCVTargetLowering()
826 setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom); in RISCVTargetLowering()
827 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in RISCVTargetLowering()
828 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in RISCVTargetLowering()
831 setOperationAction(VPOpc, VT, Custom); in RISCVTargetLowering()
875 EVT VT) const { in getSetCCResultType()
876 if (!VT.isVector()) in getSetCCResultType()
879 (VT.isScalableVector() || Subtarget.useRVVForFixedLengthVectors())) in getSetCCResultType()
880 return EVT::getVectorVT(Context, MVT::i1, VT.getVectorElementCount()); in getSetCCResultType()
881 return VT.changeVectorElementTypeToInteger(); in getSetCCResultType()
997 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, in isFPImmLegal() argument
999 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
1001 if (VT == MVT::f32 && !Subtarget.hasStdExtF()) in isFPImmLegal()
1003 if (VT == MVT::f64 && !Subtarget.hasStdExtD()) in isFPImmLegal()
1010 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const { in hasBitPreservingFPLogic()
1011 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
1012 (VT == MVT::f32 && Subtarget.hasStdExtF()) || in hasBitPreservingFPLogic()
1013 (VT == MVT::f64 && Subtarget.hasStdExtD()); in hasBitPreservingFPLogic()
1018 EVT VT) const { in getRegisterTypeForCallingConv()
1021 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getRegisterTypeForCallingConv()
1024 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT); in getRegisterTypeForCallingConv()
1029 EVT VT) const { in getNumRegistersForCallingConv()
1032 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getNumRegistersForCallingConv()
1035 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT); in getNumRegistersForCallingConv()
1093 RISCVII::VLMUL RISCVTargetLowering::getLMUL(MVT VT) { in getLMUL() argument
1094 assert(VT.isScalableVector() && "Expecting a scalable vector type"); in getLMUL()
1095 unsigned KnownSize = VT.getSizeInBits().getKnownMinValue(); in getLMUL()
1096 if (VT.getVectorElementType() == MVT::i1) in getLMUL()
1137 unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) { in getSubregIndexByMVT() argument
1138 RISCVII::VLMUL LMUL = getLMUL(VT); in getSubregIndexByMVT()
1160 unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) { in getRegClassIDForVecVT() argument
1161 if (VT.getVectorElementType() == MVT::i1) in getRegClassIDForVecVT()
1163 return getRegClassIDForLMUL(getLMUL(VT)); in getRegClassIDForVecVT()
1204 bool RISCVTargetLowering::mergeStoresAfterLegalization(EVT VT) const { in mergeStoresAfterLegalization()
1206 (VT.isFixedLengthVector() && VT.getVectorElementType() == MVT::i1); in mergeStoresAfterLegalization()
1209 static bool useRVVForFixedLengthVectorVT(MVT VT, in useRVVForFixedLengthVectorVT() argument
1211 assert(VT.isFixedLengthVector() && "Expected a fixed length vector type!"); in useRVVForFixedLengthVectorVT()
1219 if (VT.getFixedSizeInBits() > 1024 * 8) in useRVVForFixedLengthVectorVT()
1225 switch (VT.getVectorElementType().SimpleTy) { in useRVVForFixedLengthVectorVT()
1231 if (VT.getVectorNumElements() > MinVLen) in useRVVForFixedLengthVectorVT()
1254 unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); in useRVVForFixedLengthVectorVT()
1261 if (!VT.isPow2VectorType()) in useRVVForFixedLengthVectorVT()
1267 bool RISCVTargetLowering::useRVVForFixedLengthVectorVT(MVT VT) const { in useRVVForFixedLengthVectorVT()
1268 return ::useRVVForFixedLengthVectorVT(VT, Subtarget); in useRVVForFixedLengthVectorVT()
1272 static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT, in getContainerForFixedLengthVector() argument
1275 assert(((VT.isFixedLengthVector() && TLI.isTypeLegal(VT)) || in getContainerForFixedLengthVector()
1276 useRVVForFixedLengthVectorVT(VT, Subtarget)) && in getContainerForFixedLengthVector()
1281 MVT EltVT = VT.getVectorElementType(); in getContainerForFixedLengthVector()
1297 divideCeil(VT.getVectorNumElements(), MinVLen / RISCV::RVVBitsPerBlock); in getContainerForFixedLengthVector()
1303 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, in getContainerForFixedLengthVector() argument
1305 return getContainerForFixedLengthVector(DAG.getTargetLoweringInfo(), VT, in getContainerForFixedLengthVector()
1309 MVT RISCVTargetLowering::getContainerForFixedLengthVector(MVT VT) const { in getContainerForFixedLengthVector()
1310 return ::getContainerForFixedLengthVector(*this, VT, getSubtarget()); in getContainerForFixedLengthVector()
1314 static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG, in convertToScalableVector() argument
1316 assert(VT.isScalableVector() && in convertToScalableVector()
1322 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero); in convertToScalableVector()
1326 static SDValue convertFromScalableVector(EVT VT, SDValue V, SelectionDAG &DAG, in convertFromScalableVector() argument
1328 assert(VT.isFixedLengthVector() && in convertFromScalableVector()
1334 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero); in convertFromScalableVector()
1370 EVT VT, unsigned DefinedValues) const { in shouldExpandBuildVectorWithShuffles() argument
1374 bool RISCVTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const { in isShuffleMaskLegal()
1376 if (ShuffleVectorSDNode::isSplatMask(M.data(), VT)) in isShuffleMaskLegal()
1384 MVT VT = Op.getSimpleValueType(); in lowerSPLAT_VECTOR() local
1385 assert(VT.isFixedLengthVector() && "Unexpected vector!"); in lowerSPLAT_VECTOR()
1387 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerSPLAT_VECTOR()
1391 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerSPLAT_VECTOR()
1394 VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL; in lowerSPLAT_VECTOR()
1396 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerSPLAT_VECTOR()
1473 MVT VT = Op.getSimpleValueType(); in lowerBUILD_VECTOR() local
1474 assert(VT.isFixedLengthVector() && "Unexpected vector!"); in lowerBUILD_VECTOR()
1476 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerBUILD_VECTOR()
1480 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerBUILD_VECTOR()
1485 if (VT.getVectorElementType() == MVT::i1) { in lowerBUILD_VECTOR()
1488 return convertFromScalableVector(VT, VMClr, DAG, Subtarget); in lowerBUILD_VECTOR()
1493 return convertFromScalableVector(VT, VMSet, DAG, Subtarget); in lowerBUILD_VECTOR()
1554 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec, in lowerBUILD_VECTOR()
1559 assert(VT.getSizeInBits() == IntegerViaVecVT.getSizeInBits()); in lowerBUILD_VECTOR()
1560 Vec = DAG.getBitcast(VT, Vec); in lowerBUILD_VECTOR()
1569 MVT WideVecVT = VT.changeVectorElementType(MVT::i8); in lowerBUILD_VECTOR()
1588 return DAG.getSetCC(DL, VT, WideVec, VecZero, ISD::SETNE); in lowerBUILD_VECTOR()
1592 unsigned Opc = VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL in lowerBUILD_VECTOR()
1595 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerBUILD_VECTOR()
1612 VID = convertFromScalableVector(VT, VID, DAG, Subtarget); in lowerBUILD_VECTOR()
1624 VT, DL, DAG.getConstant(SplatStepVal, DL, XLenVT)); in lowerBUILD_VECTOR()
1625 VID = DAG.getNode(Opcode, DL, VT, VID, SplatStep); in lowerBUILD_VECTOR()
1629 DAG.getSplatVector(VT, DL, DAG.getConstant(Addend, DL, XLenVT)); in lowerBUILD_VECTOR()
1630 VID = DAG.getNode(Negate ? ISD::SUB : ISD::ADD, DL, VT, SplatAddend, VID); in lowerBUILD_VECTOR()
1644 unsigned EltBitSize = VT.getScalarSizeInBits(); in lowerBUILD_VECTOR()
1646 if (VT.isInteger() && EltBitSize < 64 && in lowerBUILD_VECTOR()
1689 return DAG.getBitcast(VT, Splat); in lowerBUILD_VECTOR()
1733 SDValue Vec = DAG.getSplatBuildVector(VT, DL, DominantValue); in lowerBUILD_VECTOR()
1736 MVT SelMaskTy = VT.changeVectorElementType(MVT::i1); in lowerBUILD_VECTOR()
1742 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, in lowerBUILD_VECTOR()
1752 Vec = DAG.getNode(ISD::VSELECT, DL, VT, in lowerBUILD_VECTOR()
1754 DAG.getSplatBuildVector(VT, DL, V), Vec); in lowerBUILD_VECTOR()
1764 static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Lo, in splatPartsI64WithVL() argument
1772 return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Lo, VL); in splatPartsI64WithVL()
1776 return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Lo, Hi, VL); in splatPartsI64WithVL()
1782 static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar, in splatSplitI64WithVL() argument
1789 return splatPartsI64WithVL(DL, VT, Lo, Hi, VL, DAG); in splatSplitI64WithVL()
1795 static SDValue lowerScalarSplat(SDValue Scalar, SDValue VL, MVT VT, SDLoc DL, in lowerScalarSplat() argument
1798 if (VT.isFloatingPoint()) in lowerScalarSplat()
1799 return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, VT, Scalar, VL); in lowerScalarSplat()
1812 return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Scalar, VL); in lowerScalarSplat()
1819 return splatSplitI64WithVL(DL, VT, Scalar, VL, DAG); in lowerScalarSplat()
1828 MVT VT = Op.getSimpleValueType(); in lowerVECTOR_SHUFFLE() local
1829 unsigned NumElts = VT.getVectorNumElements(); in lowerVECTOR_SHUFFLE()
1832 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerVECTOR_SHUFFLE()
1835 std::tie(TrueMask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1840 MVT SVT = VT.getVectorElementType(); in lowerVECTOR_SHUFFLE()
1874 return convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1893 VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL; in lowerVECTOR_SHUFFLE()
1895 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1903 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1956 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); in lowerVECTOR_SHUFFLE()
1958 if (VT.getScalarSizeInBits() == 8 && VT.getVectorNumElements() > 256) { in lowerVECTOR_SHUFFLE()
1967 MVT IndexVT = VT.changeTypeToInteger(); in lowerVECTOR_SHUFFLE()
2011 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2014 static SDValue getRVVFPExtendOrRound(SDValue Op, MVT VT, MVT ContainerVT, in getRVVFPExtendOrRound() argument
2017 if (VT.isScalableVector()) in getRVVFPExtendOrRound()
2018 return DAG.getFPExtendOrRound(Op, DL, VT); in getRVVFPExtendOrRound()
2019 assert(VT.isFixedLengthVector() && in getRVVFPExtendOrRound()
2022 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in getRVVFPExtendOrRound()
2044 MVT VT = Op.getSimpleValueType(); in expandUnalignedRVVLoad() local
2045 unsigned EltSizeBits = VT.getScalarSizeInBits(); in expandUnalignedRVVLoad()
2049 MVT::getVectorVT(MVT::i8, VT.getVectorElementCount() * (EltSizeBits / 8)); in expandUnalignedRVVLoad()
2055 return DAG.getMergeValues({DAG.getBitcast(VT, L), L.getValue(1)}, DL); in expandUnalignedRVVLoad()
2075 MVT VT = StoredVal.getSimpleValueType(); in expandUnalignedRVVStore() local
2076 unsigned EltSizeBits = VT.getScalarSizeInBits(); in expandUnalignedRVVStore()
2080 MVT::getVectorVT(MVT::i8, VT.getVectorElementCount() * (EltSizeBits / 8)); in expandUnalignedRVVStore()
2122 EVT VT = Op.getValueType(); in LowerOperation() local
2126 if (VT.isFixedLengthVector()) { in LowerOperation()
2136 return DAG.getBitcast(VT, DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, BVT, in LowerOperation()
2145 if (!VT.isVector() && Op0VT.isFixedLengthVector()) { in LowerOperation()
2147 SDValue BVec = DAG.getBitcast(EVT::getVectorVT(Context, VT, 1), Op0); in LowerOperation()
2148 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec, in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
2173 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2176 unsigned Imm = VT.getSizeInBits() - 1; in LowerOperation()
2180 return DAG.getNode(RISCVISD::GREV, DL, VT, Op.getOperand(0), in LowerOperation()
2181 DAG.getConstant(Imm, DL, VT)); in LowerOperation()
2185 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2186 assert(VT == Subtarget.getXLenVT() && "Unexpected custom legalization"); in LowerOperation()
2193 SDValue ShAmt = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(2), in LowerOperation()
2194 DAG.getConstant(ShAmtWidth, DL, VT)); in LowerOperation()
2196 return DAG.getNode(Opc, DL, VT, Op.getOperand(0), Op.getOperand(1), ShAmt); in LowerOperation()
2200 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2202 if (!VT.isVector()) in LowerOperation()
2206 if (VT.getVectorElementType() == MVT::i1) in LowerOperation()
2212 MVT DstEltVT = VT.getVectorElementType(); in LowerOperation()
2243 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in LowerOperation()
2265 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2267 SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT); in LowerOperation()
2279 return DAG.getNode(ISD::SRL, DL, VT, VLENB, in LowerOperation()
2280 DAG.getConstant(3 - Log2, DL, VT)); in LowerOperation()
2282 return DAG.getNode(ISD::SHL, DL, VT, VLENB, in LowerOperation()
2283 DAG.getConstant(Log2 - 3, DL, VT)); in LowerOperation()
2289 return DAG.getNode(ISD::MUL, DL, VT, VLENB, in LowerOperation()
2290 DAG.getConstant(Val / 8, DL, VT)); in LowerOperation()
2293 SDValue VScale = DAG.getNode(ISD::SRL, DL, VT, VLENB, in LowerOperation()
2294 DAG.getConstant(3, DL, VT)); in LowerOperation()
2295 return DAG.getNode(ISD::MUL, DL, VT, VScale, Op.getOperand(0)); in LowerOperation()
2302 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2307 MVT ContainerVT = VT; in LowerOperation()
2309 ContainerVT = getContainerForFixedLengthVector(VT); in LowerOperation()
2315 if (!VT.isVector() || VT.getVectorElementType() != MVT::f64 || in LowerOperation()
2319 if (!VT.isFixedLengthVector()) in LowerOperation()
2322 Src = getRVVFPExtendOrRound(Src, VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2323 return convertFromScalableVector(VT, Src, DAG, Subtarget); in LowerOperation()
2326 MVT InterVT = VT.changeVectorElementType(MVT::f32); in LowerOperation()
2331 SDValue Extend = getRVVFPExtendOrRound(IntermediateExtend, VT, ContainerVT, in LowerOperation()
2333 if (VT.isFixedLengthVector()) in LowerOperation()
2334 return convertFromScalableVector(VT, Extend, DAG, Subtarget); in LowerOperation()
2342 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2347 MVT ContainerVT = VT; in LowerOperation()
2348 if (VT.isFixedLengthVector()) { in LowerOperation()
2351 SrcContainerVT.changeVectorElementType(VT.getVectorElementType()); in LowerOperation()
2355 if (!VT.isVector() || VT.getVectorElementType() != MVT::f16 || in LowerOperation()
2359 if (!VT.isFixedLengthVector()) in LowerOperation()
2362 Src = getRVVFPExtendOrRound(Src, VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2363 return convertFromScalableVector(VT, Src, DAG, Subtarget); in LowerOperation()
2367 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2372 SDValue Round = getRVVFPExtendOrRound(IntermediateRound, VT, ContainerVT, in LowerOperation()
2375 if (VT.isFixedLengthVector()) in LowerOperation()
2376 return convertFromScalableVector(VT, Round, DAG, Subtarget); in LowerOperation()
2386 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2387 if (!VT.isVector()) in LowerOperation()
2391 MVT EltVT = VT.getVectorElementType(); in LowerOperation()
2405 VT.getVectorElementCount()); in LowerOperation()
2410 return DAG.getNode(Op.getOpcode(), DL, VT, Ext); in LowerOperation()
2416 MVT InterimFVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount()); in LowerOperation()
2418 return DAG.getNode(Op.getOpcode(), DL, VT, FExt); in LowerOperation()
2426 MVT InterimFVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount()); in LowerOperation()
2428 return DAG.getFPExtendOrRound(Int2FP, DL, VT); in LowerOperation()
2435 VT.getVectorElementCount()); in LowerOperation()
2437 return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int); in LowerOperation()
2442 if (!VT.isFixedLengthVector()) in LowerOperation()
2469 SrcContainerVT.changeVectorElementType(VT.getVectorElementType()); in LowerOperation()
2471 ContainerVT = getContainerForFixedLengthVector(VT); in LowerOperation()
2476 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2480 return convertFromScalableVector(VT, Src, DAG, Subtarget); in LowerOperation()
2519 MVT VT = Op.getSimpleValueType(); in LowerOperation() local
2522 SDValue Vec = DAG.getUNDEF(VT); in LowerOperation()
2524 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Vec, OpIdx.value(), in LowerOperation()
2891 MVT VT = Op.getSimpleValueType(); in lowerSELECT() local
2895 if (VT.isVector()) { in lowerSELECT()
2896 MVT SplatCondVT = VT.changeVectorElementType(MVT::i1); in lowerSELECT()
2897 SDValue CondSplat = VT.isScalableVector() in lowerSELECT()
2900 return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV); in lowerSELECT()
2909 if (VT == XLenVT && CondV.getOpcode() == ISD::SETCC && in lowerSELECT()
2998 EVT VT = Op.getValueType(); in lowerFRAMEADDR() local
3000 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT); in lowerFRAMEADDR()
3004 SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, in lowerFRAMEADDR()
3007 DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); in lowerFRAMEADDR()
3024 EVT VT = Op.getValueType(); in lowerRETURNADDR() local
3030 SDValue Offset = DAG.getConstant(Off, DL, VT); in lowerRETURNADDR()
3031 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in lowerRETURNADDR()
3032 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), in lowerRETURNADDR()
3048 EVT VT = Lo.getValueType(); in lowerShiftLeftParts() local
3057 SDValue Zero = DAG.getConstant(0, DL, VT); in lowerShiftLeftParts()
3058 SDValue One = DAG.getConstant(1, DL, VT); in lowerShiftLeftParts()
3059 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); in lowerShiftLeftParts()
3060 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); in lowerShiftLeftParts()
3061 SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); in lowerShiftLeftParts()
3062 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); in lowerShiftLeftParts()
3064 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
3065 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in lowerShiftLeftParts()
3067 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, XLenMinus1Shamt); in lowerShiftLeftParts()
3068 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in lowerShiftLeftParts()
3069 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); in lowerShiftLeftParts()
3070 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen); in lowerShiftLeftParts()
3072 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); in lowerShiftLeftParts()
3074 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); in lowerShiftLeftParts()
3075 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in lowerShiftLeftParts()
3087 EVT VT = Lo.getValueType(); in lowerShiftRightParts() local
3107 SDValue Zero = DAG.getConstant(0, DL, VT); in lowerShiftRightParts()
3108 SDValue One = DAG.getConstant(1, DL, VT); in lowerShiftRightParts()
3109 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); in lowerShiftRightParts()
3110 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); in lowerShiftRightParts()
3111 SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); in lowerShiftRightParts()
3112 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); in lowerShiftRightParts()
3114 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
3115 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); in lowerShiftRightParts()
3117 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt); in lowerShiftRightParts()
3118 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi); in lowerShiftRightParts()
3119 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in lowerShiftRightParts()
3120 SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen); in lowerShiftRightParts()
3122 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero; in lowerShiftRightParts()
3124 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); in lowerShiftRightParts()
3126 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); in lowerShiftRightParts()
3127 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in lowerShiftRightParts()
3138 MVT VT = Op.getSimpleValueType(); in lowerVectorMaskSplat() local
3142 SDValue VL = getDefaultScalableVLOps(VT, DL, DAG, Subtarget).second; in lowerVectorMaskSplat()
3143 return DAG.getNode(RISCVISD::VMSET_VL, DL, VT, VL); in lowerVectorMaskSplat()
3146 SDValue VL = getDefaultScalableVLOps(VT, DL, DAG, Subtarget).second; in lowerVectorMaskSplat()
3147 return DAG.getNode(RISCVISD::VMCLR_VL, DL, VT, VL); in lowerVectorMaskSplat()
3152 MVT InterVT = VT.changeVectorElementType(MVT::i8); in lowerVectorMaskSplat()
3157 return DAG.getSetCC(DL, VT, LHS, Zero, ISD::SETNE); in lowerVectorMaskSplat()
3267 MVT VT = Op.getOperand(0).getSimpleValueType(); in lowerFixedLengthVectorExtendToRVV() local
3274 MVT ContainerVT = MVT::getVectorVT(VT.getVectorElementType(), in lowerFixedLengthVectorExtendToRVV()
3282 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorExtendToRVV()
3529 MVT VT = Op.getOperand(SplatOp - 1).getSimpleValueType(); in lowerVectorIntrinsicSplats() local
3533 VT.getVectorElementType() == MVT::i64 && "Unexpected VTs!"); in lowerVectorIntrinsicSplats()
3550 ScalarOp = splatSplitI64WithVL(DL, VT, ScalarOp, VL, DAG); in lowerVectorIntrinsicSplats()
3625 MVT VT = Op.getSimpleValueType(); in LowerINTRINSIC_WO_CHAIN() local
3629 SDValue SplattedVal = splatSplitI64WithVL(DL, VT, Scalar, VL, DAG); in LowerINTRINSIC_WO_CHAIN()
3630 SDValue SplattedIdx = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, in LowerINTRINSIC_WO_CHAIN()
3633 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorElementCount()); in LowerINTRINSIC_WO_CHAIN()
3635 SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL); in LowerINTRINSIC_WO_CHAIN()
3639 return DAG.getNode(RISCVISD::VSELECT_VL, DL, VT, SelectCond, SplattedVal, in LowerINTRINSIC_WO_CHAIN()
3659 MVT VT = Op.getSimpleValueType(); in LowerINTRINSIC_WO_CHAIN() local
3660 assert(VT.getVectorElementType() == MVT::i64 && in LowerINTRINSIC_WO_CHAIN()
3664 MVT I32VT = MVT::getVectorVT(MVT::i32, VT.getVectorElementCount() * 2); in LowerINTRINSIC_WO_CHAIN()
3696 Vec = DAG.getBitcast(VT, Vec); in LowerINTRINSIC_WO_CHAIN()
3704 return DAG.getNode(RISCVISD::VSELECT_VL, DL, VT, Mask, Vec, MaskedOff, VL); in LowerINTRINSIC_WO_CHAIN()
3716 static MVT getLMUL1VT(MVT VT) { in getLMUL1VT() argument
3717 assert(VT.getVectorElementType().getSizeInBits() <= 64 && in getLMUL1VT()
3720 VT.getVectorElementType(), in getLMUL1VT()
3721 RISCV::RVVBitsPerBlock / VT.getVectorElementType().getSizeInBits()); in getLMUL1VT()
4180 MVT VT = Op.getSimpleValueType(); in lowerSTEP_VECTOR() local
4183 std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget); in lowerSTEP_VECTOR()
4184 SDValue StepVec = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL); in lowerSTEP_VECTOR()
4189 DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, in lowerSTEP_VECTOR()
4191 StepVec = DAG.getNode(ISD::SHL, DL, VT, StepVec, StepVal); in lowerSTEP_VECTOR()
4194 DAG.getConstant(StepValImm, DL, VT.getVectorElementType()), VL, VT, in lowerSTEP_VECTOR()
4196 StepVec = DAG.getNode(ISD::MUL, DL, VT, StepVec, StepVal); in lowerSTEP_VECTOR()
4291 MVT VT = Op.getSimpleValueType(); in lowerFixedLengthVectorLoadToRVV() local
4292 MVT ContainerVT = getContainerForFixedLengthVector(VT); in lowerFixedLengthVectorLoadToRVV()
4295 DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); in lowerFixedLengthVectorLoadToRVV()
4302 SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerFixedLengthVectorLoadToRVV()
4318 MVT VT = StoreVal.getSimpleValueType(); in lowerFixedLengthVectorStoreToRVV() local
4321 if (VT.getVectorElementType() == MVT::i1 && VT.getVectorNumElements() < 8) { in lowerFixedLengthVectorStoreToRVV()
4322 VT = MVT::v8i1; in lowerFixedLengthVectorStoreToRVV()
4323 StoreVal = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerFixedLengthVectorStoreToRVV()
4324 DAG.getConstant(0, DL, VT), StoreVal, in lowerFixedLengthVectorStoreToRVV()
4328 MVT ContainerVT = getContainerForFixedLengthVector(VT); in lowerFixedLengthVectorStoreToRVV()
4331 DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); in lowerFixedLengthVectorStoreToRVV()
4345 MVT VT = Op.getSimpleValueType(); in lowerMLOAD() local
4352 MVT ContainerVT = VT; in lowerMLOAD()
4353 if (VT.isFixedLengthVector()) { in lowerMLOAD()
4354 ContainerVT = getContainerForFixedLengthVector(VT); in lowerMLOAD()
4359 VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT); in lowerMLOAD()
4372 if (VT.isFixedLengthVector()) in lowerMLOAD()
4373 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerMLOAD()
4384 MVT VT = Val.getSimpleValueType(); in lowerMSTORE() local
4388 MVT ContainerVT = VT; in lowerMSTORE()
4389 if (VT.isFixedLengthVector()) { in lowerMSTORE()
4390 ContainerVT = getContainerForFixedLengthVector(VT); in lowerMSTORE()
4395 VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT); in lowerMSTORE()
4412 MVT VT = Op.getSimpleValueType(); in lowerFixedLengthVectorSetccToRVV() local
4421 DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); in lowerFixedLengthVectorSetccToRVV()
4429 return convertFromScalableVector(VT, Cmp, DAG, Subtarget); in lowerFixedLengthVectorSetccToRVV()
4434 MVT VT = Op.getSimpleValueType(); in lowerFixedLengthVectorLogicOpToRVV() local
4436 if (VT.getVectorElementType() == MVT::i1) in lowerFixedLengthVectorLogicOpToRVV()
4459 MVT VT = Op.getSimpleValueType(); in lowerABS() local
4462 assert(VT.isFixedLengthVector() && "Unexpected type"); in lowerABS()
4464 MVT ContainerVT = getContainerForFixedLengthVector(VT); in lowerABS()
4468 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerABS()
4478 return convertFromScalableVector(VT, Max, DAG, Subtarget); in lowerABS()
4484 MVT VT = Op.getSimpleValueType(); in lowerFixedLengthVectorFCOPYSIGNToRVV() local
4490 MVT ContainerVT = getContainerForFixedLengthVector(VT); in lowerFixedLengthVectorFCOPYSIGNToRVV()
4495 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
4500 return convertFromScalableVector(VT, CopySign, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
4505 MVT VT = Op.getSimpleValueType(); in lowerFixedLengthVectorSelectToRVV() local
4506 MVT ContainerVT = getContainerForFixedLengthVector(VT); in lowerFixedLengthVectorSelectToRVV()
4520 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
4525 return convertFromScalableVector(VT, Select, DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
4531 MVT VT = Op.getSimpleValueType(); in lowerToScalableOp() local
4532 MVT ContainerVT = getContainerForFixedLengthVector(VT); in lowerToScalableOp()
4553 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerToScalableOp()
4559 return convertFromScalableVector(VT, ScalableRes, DAG, Subtarget); in lowerToScalableOp()
4570 MVT VT = Op.getSimpleValueType(); in lowerVPOp() local
4589 if (!VT.isFixedLengthVector()) in lowerVPOp()
4590 return DAG.getNode(RISCVISDOpc, DL, VT, Ops); in lowerVPOp()
4592 MVT ContainerVT = getContainerForFixedLengthVector(VT); in lowerVPOp()
4596 return convertFromScalableVector(VT, VPOp, DAG, Subtarget); in lowerVPOp()
4612 MVT VT = Op.getSimpleValueType(); in lowerMGATHER() local
4616 assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() && in lowerMGATHER()
4629 MVT ContainerVT = VT; in lowerMGATHER()
4630 if (VT.isFixedLengthVector()) { in lowerMGATHER()
4633 if (VT.bitsGE(IndexVT)) { in lowerMGATHER()
4634 ContainerVT = getContainerForFixedLengthVector(VT); in lowerMGATHER()
4652 VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT); in lowerMGATHER()
4674 if (VT.isFixedLengthVector()) in lowerMGATHER()
4675 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerMGATHER()
4693 MVT VT = Val.getSimpleValueType(); in lowerMSCATTER() local
4697 assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() && in lowerMSCATTER()
4710 if (VT.isFixedLengthVector()) { in lowerMSCATTER()
4714 if (VT.bitsGE(IndexVT)) { in lowerMSCATTER()
4715 ContainerVT = getContainerForFixedLengthVector(VT); in lowerMSCATTER()
4720 ContainerVT = MVT::getVectorVT(VT.getVectorElementType(), in lowerMSCATTER()
4733 VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT); in lowerMSCATTER()
5014 MVT VT = N->getSimpleValueType(0); in ReplaceNodeResults() local
5015 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && in ReplaceNodeResults()
5028 if (VT != MVT::i32) in ReplaceNodeResults()
5082 EVT VT = N->getValueType(0); in ReplaceNodeResults() local
5083 assert(VT.isInteger() && !VT.isVector() && "Unexpected VT!"); in ReplaceNodeResults()
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5090 } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5095 } else if (!VT.isVector() && Op0VT.isFixedLengthVector() && in ReplaceNodeResults()
5102 SDValue BVec = DAG.getBitcast(EVT::getVectorVT(Context, VT, 1), Op0); in ReplaceNodeResults()
5103 Results.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec, in ReplaceNodeResults()
5144 MVT VT = N->getSimpleValueType(0); in ReplaceNodeResults() local
5146 assert((VT == MVT::i8 || VT == MVT::i16 || in ReplaceNodeResults()
5147 (VT == MVT::i32 && Subtarget.is64Bit())) && in ReplaceNodeResults()
5150 unsigned Imm = VT.getSizeInBits() - 1; in ReplaceNodeResults()
5159 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, GREVI)); in ReplaceNodeResults()
5308 EVT VT = N->getValueType(0); in ReplaceNodeResults() local
5310 if (VT.bitsLT(XLenVT)) { in ReplaceNodeResults()
5314 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract)); in ReplaceNodeResults()
5318 assert(VT == MVT::i64 && !Subtarget.is64Bit() && in ReplaceNodeResults()
5484 EVT VT = Op.getValueType(); in combineORToGREV() local
5486 if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { in combineORToGREV()
5491 return DAG.getNode(RISCVISD::GREV, DL, VT, LHS->Op, in combineORToGREV()
5492 DAG.getConstant(LHS->ShAmt, DL, VT)); in combineORToGREV()
5510 EVT VT = Op.getValueType(); in combineORToGORC() local
5512 if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { in combineORToGORC()
5521 return DAG.getNode(RISCVISD::GORC, DL, VT, X, Reverse.getOperand(1)); in combineORToGORC()
5528 if (RotAmt == (VT.getSizeInBits() / 2)) in combineORToGORC()
5529 return DAG.getNode(RISCVISD::GORC, DL, VT, X, in combineORToGORC()
5530 DAG.getConstant(RotAmt, DL, VT)); in combineORToGORC()
5557 return DAG.getNode(RISCVISD::GORC, DL, VT, LHS->Op, in combineORToGORC()
5558 DAG.getConstant(LHS->ShAmt, DL, VT)); in combineORToGORC()
5589 EVT VT = Op.getValueType(); in combineORToSHFL() local
5591 if (VT != MVT::i32 && VT != Subtarget.getXLenVT()) in combineORToSHFL()
5655 return DAG.getNode(RISCVISD::SHFL, DL, VT, Match1->Op, in combineORToSHFL()
5656 DAG.getConstant(Match1->ShAmt, DL, VT)); in combineORToSHFL()
5702 EVT VT = N->getValueType(0); in combineSelectCCAndUse() local
5726 FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal); in combineSelectCCAndUse()
5731 return DAG.getNode(RISCVISD::SELECT_CC, SDLoc(N), VT, in combineSelectCCAndUse()
5799 EVT VT = N->getValueType(0); in performANY_EXTENDCombine() local
5800 if (VT != MVT::i64 || Src.getValueType() != MVT::i32) in performANY_EXTENDCombine()
6213 EVT VT = N->getValueType(0); in PerformDAGCombine() local
6214 if (!VT.isVector()) in PerformDAGCombine()
6232 SDValue NewFPExtRound = DAG.getFPExtendOrRound(In2.getOperand(0), DL, VT); in PerformDAGCombine()
6233 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N->getOperand(0), in PerformDAGCombine()
6234 DAG.getNode(ISD::FNEG, DL, VT, NewFPExtRound)); in PerformDAGCombine()
6296 EVT VT = N->getValueType(0); in PerformDAGCombine() local
6298 DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, ShAmt.getOperand(0), VL); in PerformDAGCombine()
6299 return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt, in PerformDAGCombine()
6311 EVT VT = N->getValueType(0); in PerformDAGCombine() local
6313 DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VT, ShAmt.getOperand(0)); in PerformDAGCombine()
6314 return DAG.getNode(N->getOpcode(), DL, VT, N->getOperand(0), ShAmt); in PerformDAGCombine()
6342 MVT VT = N->getSimpleValueType(0); in PerformDAGCombine() local
6344 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() / 2), in PerformDAGCombine()
6345 VT.getVectorElementCount()); in PerformDAGCombine()
6357 return DAG.getNode(WMulOpc, DL, VT, Op0, Op1, Mask, VL); in PerformDAGCombine()
6419 EVT VT = Op.getValueType(); in targetShrinkDemandedConstant() local
6420 if (VT.isVector()) in targetShrinkDemandedConstant()
6443 auto UseMask = [Mask, Op, VT, &TLO](const APInt &NewMask) -> bool { in targetShrinkDemandedConstant()
6447 SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT); in targetShrinkDemandedConstant()
6448 SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC); in targetShrinkDemandedConstant()
6465 if (VT == MVT::i64) { in targetShrinkDemandedConstant()
7289 MVT ArgVT = ArgIdx.value().VT; in preAssignMask()
7308 MVT ArgVT = Ins[i].VT; in analyzeInputArgs()
7339 MVT ArgVT = Outs[i].VT; in analyzeOutputArgs()
7866 static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG) { in getPrefTypeAlign() argument
7868 VT.getTypeForEVT(*DAG.getContext())); in getPrefTypeAlign()
8184 MVT VT = Outs[i].VT; in CanLowerReturn() local
8187 if (CC_RISCV(MF.getDataLayout(), ABI, i, VT, VT, CCValAssign::Full, in CanLowerReturn()
8484 MVT VT) const { in getRegForInlineAsmConstraint()
8492 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
8494 if (Subtarget.hasStdExtF() && VT == MVT::f32) in getRegForInlineAsmConstraint()
8496 if (Subtarget.hasStdExtD() && VT == MVT::f64) in getRegForInlineAsmConstraint()
8503 if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) in getRegForInlineAsmConstraint()
8642 if (TRI->isTypeLegalForClass(RISCV::VMRegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
8644 if (TRI->isTypeLegalForClass(RISCV::VRRegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
8648 if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) { in getRegForInlineAsmConstraint()
8656 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); in getRegForInlineAsmConstraint()
8878 bool RISCVTargetLowering::shouldRemoveExtendFromGSIndex(EVT VT) const { in shouldRemoveExtendFromGSIndex()
8883 EVT VT) const { in isFMAFasterThanFMulAndFAdd()
8884 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
8886 if (!VT.isSimple()) in isFMAFasterThanFMulAndFAdd()
8889 switch (VT.getSimpleVT().SimpleTy) { in isFMAFasterThanFMulAndFAdd()
8930 bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, in decomposeMulByConstant() argument
8933 if (VT.isScalarInteger()) { in decomposeMulByConstant()
8936 if (Subtarget.hasStdExtM() && VT.getSizeInBits() > Subtarget.getXLen()) in decomposeMulByConstant()
8946 if (Subtarget.hasStdExtM() && VT.getSizeInBits() >= Subtarget.getXLen()) in decomposeMulByConstant()
8963 EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, in allowsMisalignedMemoryAccesses() argument
8965 if (!VT.isVector()) in allowsMisalignedMemoryAccesses()
8968 EVT ElemVT = VT.getVectorElementType(); in allowsMisalignedMemoryAccesses()
9065 RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT, in getRegisterByName() argument