Lines Matching refs:VT
187 bool isTypeLegal(Type *Ty, MVT &VT);
188 bool isLoadTypeLegal(Type *Ty, MVT &VT);
191 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
194 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
197 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
202 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
203 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
204 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
205 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
206 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
208 unsigned ARMLowerPICELF(const GlobalValue *GV, MVT VT);
236 void AddLoadStoreOperands(MVT VT, Address &Addr,
392 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { in ARMMoveToFPReg() argument
393 if (VT == MVT::f64) return 0; in ARMMoveToFPReg()
395 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
402 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { in ARMMoveToIntReg() argument
403 if (VT == MVT::i64) return 0; in ARMMoveToIntReg()
405 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
415 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { in ARMMaterializeFP() argument
417 bool is64bit = VT == MVT::f64; in ARMMaterializeFP()
421 if (TLI.isFPImmLegal(Val, VT)) { in ARMMaterializeFP()
431 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
443 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
454 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { in ARMMaterializeInt() argument
455 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) in ARMMaterializeInt()
473 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { in ARMMaterializeInt()
491 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in ARMMaterializeInt()
497 if (VT != MVT::i32) in ARMMaterializeInt()
503 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
523 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { in ARMMaterializeGV() argument
525 if (VT != MVT::i32 || GV->isThreadLocal()) return 0; in ARMMaterializeGV()
562 return ARMLowerPICELF(GV, VT); in ARMMaterializeGV()
592 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
608 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
631 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
634 return ARMMaterializeFP(CFP, VT); in fastMaterializeConstant()
636 return ARMMaterializeGV(GV, VT); in fastMaterializeConstant()
638 return ARMMaterializeInt(C, VT); in fastMaterializeConstant()
649 MVT VT; in fastMaterializeAlloca() local
650 if (!isLoadTypeLegal(AI->getType(), VT)) return 0; in fastMaterializeAlloca()
659 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
673 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal() argument
678 VT = evt.getSimpleVT(); in isTypeLegal()
682 return TLI.isTypeLegal(VT); in isTypeLegal()
685 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal() argument
686 if (isTypeLegal(Ty, VT)) return true; in isLoadTypeLegal()
690 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isLoadTypeLegal()
802 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { in ARMSimplifyAddress() argument
804 switch (VT.SimpleTy) { in ARMSimplifyAddress()
854 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr, in AddLoadStoreOperands() argument
860 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
900 bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, in ARMEmitLoad() argument
906 switch (VT.SimpleTy) { in ARMEmitLoad()
960 VT = MVT::i32; in ARMEmitLoad()
965 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
977 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
981 ARMSimplifyAddress(Addr, VT, useAM3); in ARMEmitLoad()
989 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3); in ARMEmitLoad()
1024 MVT VT; in SelectLoad() local
1025 if (!isLoadTypeLegal(I->getType(), VT)) in SelectLoad()
1033 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) in SelectLoad()
1039 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, in ARMEmitStore() argument
1043 switch (VT.SimpleTy) { in ARMEmitStore()
1103 VT = MVT::i32; in ARMEmitStore()
1121 ARMSimplifyAddress(Addr, VT, useAM3); in ARMEmitStore()
1128 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3); in ARMEmitStore()
1156 MVT VT; in SelectStore() local
1157 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) in SelectStore()
1169 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())) in SelectStore()
1600 MVT VT; in SelectSelect() local
1601 if (!isTypeLegal(I->getType(), VT)) in SelectSelect()
1605 if (VT != MVT::i32) return false; in SelectSelect()
1617 assert(VT == MVT::i32 && "Expecting an i32."); in SelectSelect()
1676 MVT VT; in SelectDiv() local
1678 if (!isTypeLegal(Ty, VT)) in SelectDiv()
1689 if (VT == MVT::i8) in SelectDiv()
1691 else if (VT == MVT::i16) in SelectDiv()
1693 else if (VT == MVT::i32) in SelectDiv()
1695 else if (VT == MVT::i64) in SelectDiv()
1697 else if (VT == MVT::i128) in SelectDiv()
1705 MVT VT; in SelectRem() local
1707 if (!isTypeLegal(Ty, VT)) in SelectRem()
1713 if (!TLI.hasStandaloneRem(VT)) { in SelectRem()
1718 if (VT == MVT::i8) in SelectRem()
1720 else if (VT == MVT::i16) in SelectRem()
1722 else if (VT == MVT::i32) in SelectRem()
1724 else if (VT == MVT::i64) in SelectRem()
1726 else if (VT == MVT::i128) in SelectRem()
1776 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp() local
1779 if (VT.isVector()) in SelectBinaryFPOp()
1793 bool is64bit = VT == MVT::f64 || VT == MVT::i64; in SelectBinaryFPOp()
1812 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
2446 MVT VT; in ARMTryEmitSmallMemCpy() local
2449 VT = MVT::i32; in ARMTryEmitSmallMemCpy()
2451 VT = MVT::i16; in ARMTryEmitSmallMemCpy()
2454 VT = MVT::i8; in ARMTryEmitSmallMemCpy()
2459 VT = MVT::i16; in ARMTryEmitSmallMemCpy()
2461 VT = MVT::i8; in ARMTryEmitSmallMemCpy()
2467 RV = ARMEmitLoad(VT, ResultReg, Src); in ARMTryEmitSmallMemCpy()
2469 RV = ARMEmitStore(VT, ResultReg, Dest); in ARMTryEmitSmallMemCpy()
2473 unsigned Size = VT.getSizeInBits()/8; in ARMTryEmitSmallMemCpy()
2913 MVT VT; in tryToFoldLoadIntoMI() local
2914 if (!isLoadTypeLegal(LI->getType(), VT)) in tryToFoldLoadIntoMI()
2930 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) { in tryToFoldLoadIntoMI()
2942 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) in tryToFoldLoadIntoMI()
2949 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, MVT VT) { in ARMLowerPICELF() argument
2978 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMLowerPICELF()
2990 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMLowerPICELF()